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S4MF03107SPZQQ1

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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S4MF03107SPZQQ1

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

S4MF03107SPZQQ1 from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MibSPI2SCS[0] bidirectional MibSPI2 slave chip select 0, 3.3-V adaptive-impedance 4 mA I/O that can be programmed as a GIO pin.
2 MibSPI2SCS[1] bidirectional MibSPI2 slave chip select 1, 3.3-V adaptive-impedance 4 mA I/O that can be programmed as a GIO pin.
3 MibSPI2SCS[2] bidirectional MibSPI2 slave chip select 2, 3.3-V adaptive-impedance 4 mA I/O that can be programmed as a GIO pin.
4 MibSPI2SCS[3] bidirectional MibSPI2 slave chip select 3, 3.3-V adaptive-impedance 4 mA I/O that can be programmed as a GIO pin.
5 GIOA[4]/INT[4] bidirectional General-purpose I/O with interrupt capability, 3.3-V adaptive-impedance 4 mA, programmable internal pulldown (100 µA).
6 GIOA[5]/INT[5] bidirectional General-purpose I/O with interrupt capability, 3.3-V adaptive-impedance 4 mA, programmable internal pulldown (100 µA).
7 CAN1STX bidirectional DCAN1 transmit pin or GIO pin, 3.3-V adaptive-impedance 4 mA, programmable internal pullup (100 µA).
8 CAN1SRX bidirectional DCAN1 receive pin or GIO pin, 3.3-V adaptive-impedance 4 mA, programmable internal pullup (100 µA).
9 VSS power_in Digital I/O and core supply ground reference.
10 OSCIN input Crystal connection pin or external clock input (1.55-V).
11 OSCOUT output External crystal connection pin (1.55-V).
12 VCC power_in 1.55-V core supply: Vreg output when the regulator is enabled, input when the regulator is disabled.
13 VSS power_in Digital I/O and core supply ground reference.
14 VCCIOR power_in 3.3-V digital I/O and internal regulator supply voltage.
15 GIOA[6]/INT[6] bidirectional General-purpose I/O with interrupt capability, 3.3-V adaptive-impedance 4 mA, programmable internal pulldown (100 µA).
16 GIOA[7]/INT[7] bidirectional General-purpose I/O with interrupt capability, 3.3-V adaptive-impedance 4 mA, programmable internal pulldown (100 µA).
17 MibSPI2CLK bidirectional MibSPI2 clock, can be programmed as a GIO pin.
18 MibSPI2SIMO bidirectional MibSPI2 slave in/master out data stream, can be programmed as a GIO pin.
19 MibSPI2SOMI bidirectional MibSPI2 slave out/master in data stream, can be programmed as a GIO pin.
20 VCCIOR power_in 3.3-V digital I/O and internal regulator supply voltage.
21 VSS power_in Digital I/O and core supply ground reference.
22 LIN1SCI1TX bidirectional LIN/SCI1 data transmit, can be programmed as a GIO pin.
23 LIN1SCI1RX bidirectional LIN/SCI1 data receive, can be programmed as a GIO pin.
24 LIN2SCI2TX bidirectional LIN/SCI2 data transmit, can be programmed as a GIO pin.
25 LIN2SCI2RX bidirectional LIN/SCI2 data receive, can be programmed as a GIO pin.
26 MIBSPI1SCS[7] bidirectional MibSPI1 slave chip select 7, can be programmed as a GIO pin.
27 MIBSPI1SCS[6] bidirectional MibSPI1 slave chip select 6, can be programmed as a GIO pin.
28 MIBSPI1SCS[5] bidirectional MibSPI1 slave chip select 5, can be programmed as a GIO pin.
29 MIBSPI1SCS[4] bidirectional MibSPI1 slave chip select 4, can be programmed as a GIO pin.
30 MIBSPI1SCS[3] bidirectional MibSPI1 slave chip select 3, can be programmed as a GIO pin.
31 MIBSPI1SCS[2] bidirectional MibSPI1 slave chip select 2, can be programmed as a GIO pin.
32 MIBSPI1SCS[1] bidirectional MibSPI1 slave chip select 1, can be programmed as a GIO pin.
33 MIBSPI1SCS[0] bidirectional MibSPI1 slave chip select 0, can be programmed as a GIO pin.
34 MIBSPI1CLK bidirectional MibSPI1 clock, can be programmed as a GIO pin.
35 MIBSPI1SIMO bidirectional MibSPI1 slave in/master out data stream, can be programmed as a GIO pin.
36 MIBSPI1SOMI bidirectional MibSPI1 slave out/master in data stream, can be programmed as a GIO pin.
37 CAN2STX bidirectional DCAN2 transmit pin or GIO pin, 3.3-V adaptive-impedance 4 mA, programmable internal pullup (100 µA).
38 CAN2SRX bidirectional DCAN2 receive pin or GIO pin, 3.3-V adaptive-impedance 4 mA, programmable internal pullup (100 µA).
39 HET[0] bidirectional Timer input capture or output compare, programmable as GIO, 3.3-V adaptive-impedance 4 mA with internal pulldown (100 µA).
40 HET[1] bidirectional Timer input capture or output compare, programmable as GIO, 3.3-V adaptive-impedance 4 mA with internal pulldown (100 µA).
41 VCC power_in 1.55-V core supply: Vreg output when the regulator is enabled, input when the regulator is disabled.
42 VSS power_in Digital I/O and core supply ground reference.
43 VCCIOR power_in 3.3-V digital I/O and internal regulator supply voltage.
44 TCK input JTAG test clock that controls the test hardware, 3.3-V input with internal pulldown (100 µA).
45 TDO output JTAG test data out, outputs serial data from the instruction, data and identification registers; 3.3-V adaptive-impedance 4 mA.
46 TDI input JTAG test data in, inputs serial data to the test instruction and data registers; internal pullup (100 µA).
47 TMS input JTAG serial input controlling the state of the CPU test access port (TAP) controller; internal pullup (100 µA).
48 TRST input Test hardware reset to TAP (IEEE 1149.1 boundary-scan logic), 3.3-V input with internal pulldown (100 µA).
49 HET[2] bidirectional Timer input capture or output compare, programmable as GIO, 3.3-V adaptive-impedance 4 mA with internal pulldown (100 µA).
50 HET[3] bidirectional Timer input capture or output compare, programmable as GIO, 3.3-V adaptive-impedance 4 mA with internal pulldown (100 µA).
51 VSS power_in Digital I/O and core supply ground reference.
52 VCCIOR power_in 3.3-V digital I/O and internal regulator supply voltage.
53 HET[4] bidirectional Timer input capture or output compare, programmable as GIO, 3.3-V adaptive-impedance 4 mA with internal pulldown (100 µA).
54 HET[5] bidirectional Timer input capture or output compare, programmable as GIO, 3.3-V adaptive-impedance 4 mA with internal pulldown (100 µA).
55 HET[6] bidirectional Timer input capture or output compare, programmable as GIO, 3.3-V adaptive-impedance 4 mA with internal pulldown (100 µA).
56 HET[7] bidirectional Timer input capture or output compare, programmable as GIO, 3.3-V adaptive-impedance 4 mA with internal pulldown (100 µA).
57 HET[8] bidirectional Timer input capture or output compare, programmable as GIO, 3.3-V adaptive-impedance 4 mA with internal pulldown (100 µA).
58 HET[9] bidirectional Timer input capture or output compare, programmable as GIO, 3.3-V adaptive-impedance 4 mA with internal pulldown (100 µA).
59 HET[10] bidirectional Timer input capture or output compare, programmable as GIO, 3.3-V adaptive-impedance 4 mA with internal pulldown (100 µA).
60 HET[11] bidirectional Timer input capture or output compare, programmable as GIO, 3.3-V adaptive-impedance 4 mA with internal pulldown (100 µA).
61 HET[12] bidirectional Timer input capture or output compare, programmable as GIO, 3.3-V adaptive-impedance 4 mA with internal pulldown (100 µA).
62 HET[13] bidirectional Timer input capture or output compare, programmable as GIO, 3.3-V adaptive-impedance 4 mA with internal pulldown (100 µA).
63 HET[14] bidirectional Timer input capture or output compare, programmable as GIO, 3.3-V adaptive-impedance 4 mA with internal pulldown (100 µA).
64 HET[15]/ECLK2 bidirectional HET channel 15 muxed with ECLK2 output; when ECLK2 is enabled via SYSPC1, ECLK2 is output here and HET[15] becomes internal only.
65 VCCIOR power_in 3.3-V digital I/O and internal regulator supply voltage.
66 VSS power_in Digital I/O and core supply ground reference.
67 VCC power_in 1.55-V core supply: Vreg output when the regulator is enabled, input when the regulator is disabled.
68 ADEVT bidirectional MibADC event input, can be programmed as a GIO pin; 3.3-V adaptive-impedance 4 mA with internal pulldown (100 µA).
69 ADIN[0] input 3.3 V MibADC analog input pin.
70 ADIN[1] input 3.3 V MibADC analog input pin.
71 ADIN[2] input 3.3 V MibADC analog input pin.
72 ADIN[3] input 3.3 V MibADC analog input pin.
73 ADIN[4] input 3.3 V MibADC analog input pin.
74 ADIN[5] input 3.3 V MibADC analog input pin.
75 ADIN[6] input 3.3 V MibADC analog input pin.
76 ADIN[7] input 3.3 V MibADC analog input pin.
77 ADIN[8] input 3.3 V MibADC analog input pin.
78 ADIN[9] input 3.3 V MibADC analog input pin.
79 ADIN[10] input 3.3 V MibADC analog input pin.
80 ADIN[11] input 3.3 V MibADC analog input pin.
81 ADIN[12] input 3.3 V MibADC analog input pin.
82 ADREFHI input MibADC module high-voltage reference input (3.3-V REF).
83 ADREFLO input MibADC module low-voltage reference input (GND REF).
84 VSSAD power_in MibADC analog ground reference.
85 VCCAD power_in MibADC analog supply voltage (3.3 V).
86 ADIN[13] input 3.3 V MibADC analog input pin.
87 ADIN[14] input 3.3 V MibADC analog input pin.
88 ADIN[15] input 3.3 V MibADC analog input pin.
89 PORRST input Input master chip power-up reset; external VCC monitor circuitry must assert a power-on reset; internal pulldown (100 µA).
90 MibSPI2ENA bidirectional MibSPI2 enable pin, can be programmed as a GIO pin; 3.3-V adaptive-impedance 4 mA, internal pullup (100 µA).
91 ENZ input Enables internal voltage regulator at 0 V and disables it at 3.3 V; intended for testing, not for disabling the regulator in application use.
92 VCC power_in 1.55-V core supply: Vreg output when the regulator is enabled, input when the regulator is disabled.
93 VSS power_in Digital I/O and core supply ground reference.
94 VCCIOR power_in 3.3-V digital I/O and internal regulator supply voltage.
95 VCCP power_in Flash external pump voltage (3.3 V), required for Flash read, program and erase; VCCP1 and VCCP2 are double bonded to this pin.
96 ECLK bidirectional Bidirectional external clock pin that can be programmed as a GIO pin; internal pulldown (100 µA).
97 TEST input Test enable reserved for internal use; TI recommends connecting to ground or pulling down to ground with an external resistor.
98 RST bidirectional Bidirectional reset with open-drain output (drives low only); TI recommends an external pullup resistor; internal pullup (100 µA).
99 FLTP1 passive Flash Test Pad 1; must connect only to a test pad (not exposed in the final product) or be left unconnected.
100 VSS power_in Digital I/O and core supply ground reference.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: S4MF03107SPZQQ1
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: s4mf03107spzqq1-etched.step / s4mf03107spzqq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); s4mf03107spzqq1.step / s4mf03107spzqq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (71 pp, sha256 b26b6828cf4d2894, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF