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Contents

README

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CD74ACT299M96

Texas Instruments · Shift Registers · SOIC-20-300mil

CD74ACT299M96 from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S0 input Mode select 0; together with S1 selects hold, shift right, shift left or parallel load, and when S0 and S1 are both high the I/O pins are high-impedance inputs.
2 !OE1 input Active-low output enable 1; when high the I/O terminals are forced to the off (high-impedance) state.
3 !OE2 input Active-low output enable 2; when high the I/O terminals are forced to the off (high-impedance) state.
4 I/O6 bidirectional Parallel data input/output 6, a three-state output and CMOS-buffered input.
5 I/O4 bidirectional Parallel data input/output 4, a three-state output and CMOS-buffered input.
6 I/O2 bidirectional Parallel data input/output 2, a three-state output and CMOS-buffered input.
7 I/O0 bidirectional Parallel data input/output 0, a three-state output and CMOS-buffered input.
8 Q0 output Serial output from the first register stage, used for cascading to the DS7 input of the previous register.
9 !MR input Master reset, active low; on the 299 it asynchronously clears the register regardless of all other inputs.
10 GND power_in Ground.
11 DS0 input Serial data input for right shift, sampled on the low-to-high transition of CP.
12 CP input Clock input, rising-edge triggered; mode select, serial data and parallel data respond only to its low-to-high transition.
13 I/O1 bidirectional Parallel data input/output 1, a three-state output and CMOS-buffered input.
14 I/O3 bidirectional Parallel data input/output 3, a three-state output and CMOS-buffered input.
15 I/O5 bidirectional Parallel data input/output 5, a three-state output and CMOS-buffered input.
16 I/O7 bidirectional Parallel data input/output 7, a three-state output and CMOS-buffered input.
17 Q7 output Serial output from the last register stage, used for cascading to the DS0 input of the next register.
18 DS7 input Serial data input for left shift, sampled on the low-to-high transition of CP.
19 S1 input Mode select 1; together with S0 selects hold, shift right, shift left or parallel load.
20 VCC power_in Positive supply; 4.5 V to 5.5 V recommended for ACT types, with a 0.1 µF bypass capacitor placed close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: CD74ACT299M96
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: cd74act299m96-etched.step / cd74act299m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74act299m96.step / cd74act299m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 fbcafb13deed4fbf, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF