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ADS6244IRGZR

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Texas Instruments Analog To Digital Converters (ADC), QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ADS6244IRGZR

Texas Instruments · Analog To Digital Converters (ADC) · QFN-48-EP(7x7)

ADS6244IRGZR from Texas Instruments, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LGND power_in Digital ground.
2 LVDD power_in Digital power supply with operating range 3.0V to 3.6V.
3 CAP passive Connect 2nF capacitor from pin to ground.
4 RESET input Serial interface reset input; apply high-going pulse in serial mode to initialize internal registers or tie permanently high in parallel mode; has internal pull-down resistor.
5 LVDD power_in Digital power supply with operating range 3.0V to 3.6V.
6 AGND power_in Analog ground.
7 AVDD power_in Analog power supply with operating range 3.0V to 3.6V.
8 AGND power_in Analog ground.
9 AGND power_in Analog ground.
10 INA_M input Differential input signal pair channel A minus; must tie to VCM if unused to avoid floating.
11 INA_P input Differential input signal pair channel A plus; must tie to VCM if unused to avoid floating.
12 AGND power_in Analog ground.
13 AVDD power_in Analog power supply with operating range 3.0V to 3.6V.
14 NC unconnected Do not connect.
15 CFG4 input Parallel input pin controlling data format (MSB/LSB first) and 2s complement/offset binary mode selection per Table 12.
16 VCM bidirectional Common-mode voltage output in internal reference mode or reference voltage input (1.45V to 1.55V) in external reference mode.
17 AGND power_in Analog ground.
18 CLKP input Differential input clock pair plus with 0.4Vpp to 1.5Vpp sine wave, ±0.8Vpp LVPECL, ±0.35Vpp LVDS, or 3.3Vpp LVCMOS amplitude.
19 CLKM input Differential input clock pair minus with 0.4Vpp to 1.5Vpp sine wave, ±0.8Vpp LVPECL, ±0.35Vpp LVDS, or 3.3Vpp LVCMOS amplitude.
20 AGND power_in Analog ground.
21 CFG3 input Reserved pin, must tie to ground.
22 CFG2 input Parallel input pin controlling 14x/16x serialization and SDR bit clock capture edge selection per Table 10.
23 CFG1 input Parallel input pin controlling 1-wire/2-wire interface and DDR/SDR bit clock selection; tie to AVDD for 2-wire interface with DDR bit clock per Table 9.
24 AVDD power_in Analog power supply with operating range 3.0V to 3.6V.
25 AGND power_in Analog ground.
26 INB_P input Differential input signal pair channel B plus; must tie to VCM if unused to avoid floating.
27 INB_M input Differential input signal pair channel B minus; must tie to VCM if unused to avoid floating.
28 AGND power_in Analog ground.
29 AGND power_in Analog ground.
30 PDNB input Channel B ADC power down control pin; assert high to power down channel B.
31 PDNA input Channel A ADC power down control pin; assert high to power down channel A.
32 SEN input Serial interface enable input when RESET is low; controls coarse gain and internal/external reference mode when RESET is high; has internal pull-up resistor.
33 SDATA input Serial interface data input when RESET is low; controls SYNC/DESKEW/global power down when RESET is high per Table 5; has internal pull-down resistor.
34 SCLK input Serial interface clock input when RESET is low; controls SYNC/DESKEW/global power down when RESET is high per Table 5; has internal pull-down resistor.
35 LGND power_in Digital ground.
36 LVDD power_in Digital power supply with operating range 3.0V to 3.6V.
37 DB1_P output Channel B differential LVDS data output pair wire 1, positive; output maximum 10pF load capacitance without internal termination or 10pF with internal termination.
38 DB1_M output Channel B differential LVDS data output pair wire 1, minus; output maximum 10pF load capacitance without internal termination or 10pF with internal termination.
39 DB0_P output Channel B differential LVDS data output pair wire 0, plus; output maximum 10pF load capacitance without internal termination or 10pF with internal termination.
40 DB0_M output Channel B differential LVDS data output pair wire 0, minus; output maximum 10pF load capacitance without internal termination or 10pF with internal termination.
41 FCLKP output Differential frame clock output pair, plus; serialized output with programmable termination.
42 FCLKM output Differential frame clock output pair, minus; serialized output with programmable termination.
43 DCLKP output Differential bit clock output pair, plus; derived from internal PLL multiplying input clock.
44 DCLKM output Differential bit clock output pair, minus; derived from internal PLL multiplying input clock.
45 DA1_P output Channel A differential LVDS data output pair wire 1, plus; output maximum 10pF load capacitance without internal termination or 10pF with internal termination.
46 DA1_M output Channel A differential LVDS data output pair wire 1, minus; output maximum 10pF load capacitance without internal termination or 10pF with internal termination.
47 DA0_P output Channel A differential LVDS data output pair wire 0, plus; output maximum 10pF load capacitance without internal termination or 10pF with internal termination.
48 DA0_M output Channel A differential LVDS data output pair wire 0, minus; output maximum 10pF load capacitance without internal termination or 10pF with internal termination.
49 PAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-48-EP(7x7)
Category Data Acquisition
Pins 49

CAD (KiCad official)

  • Symbol: ADS6244IRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ads6244irgzr-etched.step / ads6244irgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads6244irgzr.step / ads6244irgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (76 pp, sha256 fc1d51fd33d78c79, retrieved 2026-10-01, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF