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DDTA115ECA-7-F

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Diodes Incorporated Digital Transistors, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

markdown

DDTA115ECA-7-F

Diodes Incorporated · Digital Transistors · SOT-23

DDTA115ECA-7-F from Diodes Incorporated, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN input Input (base) through built-in 100kΩ R1, with absolute maximum input voltage VIN of +10 to -40 V referenced to pin 2 for DDTA115ECA.
2 GND (+) power_in Ground/emitter reference pin (+) of the PNP pre-biased transistor, to which VIN and VCC are referenced.
3 OUT output Output (collector) with absolute maximum VCC of -50 V to pin 2 and output current IO of -20 mA for DDTA115ECA.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-23
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Resistor Tolerance R1 -30 30 % 2
Resistance Ratio Tolerance R2/R1 0.8 1 1.2 % 2
Input Resistor R1, R2 nominal R1, R2 100 kΩ DDTA115ECA (NOM) 1
Input Voltage (off) Vl(off) -1.1 -0.5 V VCC = -5V, IO = -100µA 2
Input Voltage (on) Vl(on) -3 -1.9 V VO = -0.3V, IO = -1mA, DDTA115ECA 2
Output Voltage VO(on) -0.1 -0.3 V IO/Il = -5mA/-0.25mA, DDTA115ECA 2
Input Current Il -0.15 mA VI = -5V, DDTA115ECA 2
Output Current (off) IO(off) -0.5 µA VCC = -50V, VI = 0V 2
DC Current Gain Gl 82 VO = -5V, IO = -5mA, DDTA115ECA 2
Gain-Bandwidth Product fT 250 MHz VCE = -10V, IE = -5mA, f = 100MHz 2
Supply Voltage VCC -50 V Pin 3 to 2, TA = +25°C 2
Input Voltage VIN -40 10 V DDTA115ECA, Pin 1 to 2, printed +10 to -40 2
Output Current IO -20 mA DDTA115ECA 2
Output Current IC (Max) IC -100 mA 2
Power Dissipation PD 200 mW Note 7, TA = +25°C 2
Thermal Resistance, Junction to Ambient Air RθJA 625 °C/W Note 7: FR-4 PC board, minimum recommended pad layout 2
Operating and Storage Temperature Range TJ, TSTG -55 150 °C 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin  Terminals: Finish, Matte Tin Plated Leads, Solderable per MIL-STD-202, Method 208 1

CAD (KiCad official)

  • Symbol: DDTA115ECA-7-F
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: ddta115eca-7-f-etched.step / ddta115eca-7-f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ddta115eca-7-f.step / ddta115eca-7-f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (5 pp, sha256 238b94f121ac7005, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF