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TPS54110PWPR
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Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS54110PWPR
Texas Instruments · DC-DC Converters · HTSSOP-20-EP
TPS54110PWPR from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog ground, internally connected to the sensitive analog-ground circuitry; connect to PGND and the PowerPAD. |
| 2 | VSENSE | input | Error amplifier inverting input; absolute maximum voltage range on this pin is -0.3 V to 4 V. |
| 3 | COMP | output | Error amplifier output; connect the compensation network from COMP to VSENSE. Absolute maximum sink current is 6 mA. |
| 4 | PWRGD | output | Power-good open-drain output that is high when VSENSE is at or above 93% of Vref and low otherwise; it is also low when SS/ENA is low or internal shutdown is active, with a maximum sink current of 10 mA. |
| 5 | BOOT | input | Bootstrap input; a 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates the floating drive for the high-side FET driver. |
| 6 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum sink current is 3.5 A. |
| 7 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum sink current is 3.5 A. |
| 8 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum sink current is 3.5 A. |
| 9 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum sink current is 3.5 A. |
| 10 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum sink current is 3.5 A. |
| 11 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, AGND, and the PowerPAD. |
| 12 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, AGND, and the PowerPAD. |
| 13 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, AGND, and the PowerPAD. |
| 14 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator; recommended operating input range is 3 V to 6 V, bypassed to PGND with a 1-µF to 10-µF low-ESR ceramic capacitor. |
| 15 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator; recommended operating input range is 3 V to 6 V, bypassed to PGND with a 1-µF to 10-µF low-ESR ceramic capacitor. |
| 16 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator; recommended operating input range is 3 V to 6 V, bypassed to PGND with a 1-µF to 10-µF low-ESR ceramic capacitor. |
| 17 | VBIAS | power_out | Internal bias regulator output supplying internal circuitry; bypass to AGND with a 0.1-µF to 1-µF high-quality, low-ESR ceramic capacitor. |
| 18 | SS/ENA | bidirectional | Slow-start/enable pin that acts as a logic input to enable or disable device operation and as a capacitor input to externally set the start-up time; absolute maximum sink current is 10 mA. |
| 19 | SYNC | input | Synchronization input that synchronizes to an external oscillator or selects between two internally set switching frequencies; when synchronizing externally, a resistor must be connected to RT. |
| 20 | RT | input | Frequency-setting resistor input; connect a resistor from RT to AGND to set the switching frequency fs (absolute maximum range -0.3 V to 6 V). |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Supply Chip |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
TPS54110PWPR - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps54110pwpr-etched.step/tps54110pwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54110pwpr.step/tps54110pwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (37 pp, sha256
36399588e3462175, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).