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STM32F401RCT6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32F401RCT6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
STM32F401RCT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Battery backup supply input (1.65-3.6 V) that powers the RTC, LSE oscillator and backup registers when VDD is not present. |
| 2 | PC13 | bidirectional | 5V-tolerant I/O supplied through the backup-domain power switch (limited to 3 mA, max 2 MHz with 30 pF load, must not be used to drive an LED) offering RTC_TAMP1, RTC_OUT, RTC_TS alternate functions or EVENTOUT. |
| 3 | PC14-OSC32_IN (PC14) | bidirectional | 5V-tolerant I/O (except in oscillator mode) supplied through the backup-domain power switch, usable as the 32.768 kHz LSE crystal oscillator input (OSC32_IN) or EVENTOUT. |
| 4 | PC15-OSC32_OUT (PC15) | bidirectional | 5V-tolerant I/O (except in oscillator mode) supplied through the backup-domain power switch, usable as the 32.768 kHz LSE crystal oscillator output (OSC32_OUT) or EVENTOUT. |
| 5 | PH0-OSC_IN (PH0) | bidirectional | 5V-tolerant I/O (except in oscillator mode) usable as the 4-26 MHz HSE crystal/ceramic resonator oscillator input (OSC_IN) or EVENTOUT. |
| 6 | PH1-OSC_OUT (PH1) | bidirectional | 5V-tolerant I/O (except in oscillator mode) usable as the 4-26 MHz HSE crystal/ceramic resonator oscillator output (OSC_OUT) or EVENTOUT. |
| 7 | NRST | bidirectional | Bidirectional reset pin with an embedded weak pull-up resistor; holding it low resets the device, and it outputs a reset pulse of at least 20 µs when an internal reset source triggers. |
| 8 | PC0 | bidirectional | 5V-tolerant I/O usable as ADC1_IN10 analog input or EVENTOUT. |
| 9 | PC1 | bidirectional | 5V-tolerant I/O usable as ADC1_IN11 analog input or EVENTOUT. |
| 10 | PC2 | bidirectional | 5V-tolerant I/O usable as SPI2_MISO, I2S2ext_SD, ADC1_IN12 analog input, or EVENTOUT. |
| 11 | PC3 | bidirectional | 5V-tolerant I/O usable as SPI2_MOSI/I2S2_SD, ADC1_IN13 analog input, or EVENTOUT. |
| 12 | VSSA/VREF- | power_in | Analog ground and ADC negative reference supply pin. |
| 13 | VDDA/VREF+ | power_in | Analog power supply (1.7-3.6 V) for the ADC, reset block, RC oscillators and PLL, internally tied to VREF+, with VDDA-VREF+ required to be less than 1.2 V. |
| 14 | PA0 | bidirectional | 5V-tolerant I/O usable as USART2_CTS, TIM2_CH1/TIM2_ETR, TIM5_CH1, ADC1_IN0 analog input, or WKUP wakeup-from-Standby input, or EVENTOUT. |
| 15 | PA1 | bidirectional | 5V-tolerant I/O usable as USART2_RTS, TIM2_CH2, TIM5_CH2, ADC1_IN1 analog input, or EVENTOUT. |
| 16 | PA2 | bidirectional | 5V-tolerant I/O usable as USART2_TX, TIM2_CH3, TIM5_CH3, TIM9_CH1, ADC1_IN2 analog input, or EVENTOUT. |
| 17 | PA3 | bidirectional | 5V-tolerant I/O usable as USART2_RX, TIM2_CH4, TIM5_CH4, TIM9_CH2, ADC1_IN3 analog input, or EVENTOUT. |
| 18 | VSS | power_in | Digital ground supply pin. |
| 19 | VDD | power_in | Digital power supply pin, standard operating voltage 1.7-3.6 V (1.8-3.6 V with the internal regulator enabled). |
| 20 | PA4 | bidirectional | 5V-tolerant I/O usable as SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK, ADC1_IN4 analog input, or EVENTOUT. |
| 21 | PA5 | bidirectional | 5V-tolerant I/O usable as SPI1_SCK, TIM2_CH1/TIM2_ETR, ADC1_IN5 analog input, or EVENTOUT. |
| 22 | PA6 | bidirectional | 5V-tolerant I/O usable as SPI1_MISO, TIM1_BKIN, TIM3_CH1, ADC1_IN6 analog input, or EVENTOUT. |
| 23 | PA7 | bidirectional | 5V-tolerant I/O usable as SPI1_MOSI, TIM1_CH1N, TIM3_CH2, ADC1_IN7 analog input, or EVENTOUT. |
| 24 | PC4 | bidirectional | 5V-tolerant I/O usable as ADC1_IN14 analog input or EVENTOUT. |
| 25 | PC5 | bidirectional | 5V-tolerant I/O usable as ADC1_IN15 analog input or EVENTOUT. |
| 26 | PB0 | bidirectional | 5V-tolerant I/O usable as TIM1_CH2N, TIM3_CH3, ADC1_IN8 analog input, or EVENTOUT. |
| 27 | PB1 | bidirectional | 5V-tolerant I/O usable as TIM1_CH3N, TIM3_CH4, ADC1_IN9 analog input, or EVENTOUT. |
| 28 | PB2 | bidirectional | 5V-tolerant I/O usable as BOOT1, the second boot-mode select signal sampled together with BOOT0 at reset, or EVENTOUT. |
| 29 | PB10 | bidirectional | 5V-tolerant I/O usable as SPI2_SCK/I2S2_CK, I2C2_SCL, TIM2_CH3, or EVENTOUT. |
| 30 | VCAP_1 | power_in | External regulator decoupling pin requiring a 2.2 µF ceramic capacitor (ESR < 2 Ω) to stabilize the 1.2 V internal logic supply (replaced by a 100 nF capacitor if the regulator is bypassed). |
| 31 | VSS | power_in | Digital ground supply pin. |
| 32 | VDD | power_in | Digital power supply pin, standard operating voltage 1.7-3.6 V (1.8-3.6 V with the internal regulator enabled). |
| 33 | PB12 | bidirectional | 5V-tolerant I/O usable as SPI2_NSS/I2S2_WS, I2C2_SMBA, TIM1_BKIN, or EVENTOUT. |
| 34 | PB13 | bidirectional | 5V-tolerant I/O usable as SPI2_SCK/I2S2_CK, TIM1_CH1N, or EVENTOUT. |
| 35 | PB14 | bidirectional | 5V-tolerant I/O usable as SPI2_MISO, I2S2ext_SD, TIM1_CH2N, or EVENTOUT. |
| 36 | PB15 | bidirectional | 5V-tolerant I/O usable as SPI2_MOSI/I2S2_SD, TIM1_CH3N, RTC_REFIN reference clock input, or EVENTOUT. |
| 37 | PC6 | bidirectional | 5V-tolerant I/O usable as I2S2_MCK, USART6_TX, TIM3_CH1, SDIO_D6, or EVENTOUT. |
| 38 | PC7 | bidirectional | 5V-tolerant I/O usable as I2S3_MCK, USART6_RX, TIM3_CH2, SDIO_D7, or EVENTOUT. |
| 39 | PC8 | bidirectional | 5V-tolerant I/O usable as USART6_CK, TIM3_CH3, SDIO_D0, or EVENTOUT. |
| 40 | PC9 | bidirectional | 5V-tolerant I/O usable as I2S_CKIN, I2C3_SDA, TIM3_CH4, SDIO_D1, MCO_2 microcontroller clock output, or EVENTOUT. |
| 41 | PA8 | bidirectional | 5V-tolerant I/O usable as MCO_1 microcontroller clock output, I2C3_SCL, USART1_CK, TIM1_CH1, OTG_FS_SOF, or EVENTOUT. |
| 42 | PA9 | bidirectional | 5V-tolerant I/O usable as I2C3_SMBA, USART1_TX, TIM1_CH2, OTG_FS_VBUS sensing input, or EVENTOUT. |
| 43 | PA10 | bidirectional | 5V-tolerant I/O usable as USART1_RX, TIM1_CH3, OTG_FS_ID, or EVENTOUT; this pin has a lower-value weak pull-up/pull-down (7-14 kΩ) associated with OTG_FS_ID. |
| 44 | PA11 | bidirectional | 5V-tolerant I/O usable as USART1_CTS, USART6_TX, TIM1_CH4, OTG_FS_DM (USB D-), or EVENTOUT. |
| 45 | PA12 | bidirectional | 5V-tolerant I/O usable as USART1_RTS, USART6_RX, TIM1_ETR, OTG_FS_DP (USB D+), or EVENTOUT. |
| 46 | PA13 (JTMS-SWDIO) | bidirectional | 5V-tolerant I/O whose default function is JTMS-SWDIO debug data/mode select, also selectable as EVENTOUT. |
| 47 | VSS | power_in | Digital ground supply pin. |
| 48 | VDD | power_in | Digital power supply pin, standard operating voltage 1.7-3.6 V (1.8-3.6 V with the internal regulator enabled). |
| 49 | PA14 (JTCK-SWCLK) | bidirectional | 5V-tolerant I/O whose default function is JTCK-SWCLK debug clock, also selectable as EVENTOUT. |
| 50 | PA15 (JTDI) | bidirectional | 5V-tolerant I/O whose default function is JTDI debug data input, also usable as SPI1_NSS, SPI3_NSS/I2S3_WS, TIM2_CH1/TIM2_ETR, or EVENTOUT. |
| 51 | PC10 | bidirectional | 5V-tolerant I/O usable as SPI3_SCK/I2S3_CK, SDIO_D2, or EVENTOUT. |
| 52 | PC11 | bidirectional | 5V-tolerant I/O usable as I2S3ext_SD, SPI3_MISO, SDIO_D3, or EVENTOUT. |
| 53 | PC12 | bidirectional | 5V-tolerant I/O usable as SPI3_MOSI/I2S3_SD, SDIO_CK, or EVENTOUT. |
| 54 | PD2 | bidirectional | 5V-tolerant I/O usable as TIM3_ETR, SDIO_CMD, or EVENTOUT. |
| 55 | PB3 (JTDO-SWO) | bidirectional | 5V-tolerant I/O whose default function is JTDO-SWO debug trace output, also usable as SPI1_SCK, SPI3_SCK/I2S3_CK, I2C2_SDA, TIM2_CH2, or EVENTOUT. |
| 56 | PB4 (NJTRST) | bidirectional | 5V-tolerant I/O whose default function is NJTRST debug reset, also usable as SPI1_MISO, SPI3_MISO, I2S3ext_SD, I2C3_SDA, TIM3_CH1, or EVENTOUT. |
| 57 | PB5 | bidirectional | 5V-tolerant I/O usable as SPI1_MOSI, SPI3_MOSI/I2S3_SD, I2C1_SMBA, TIM3_CH2, or EVENTOUT. |
| 58 | PB6 | bidirectional | 5V-tolerant I/O usable as I2C1_SCL, USART1_TX, TIM4_CH1, or EVENTOUT. |
| 59 | PB7 | bidirectional | 5V-tolerant I/O usable as I2C1_SDA, USART1_RX, TIM4_CH2, or EVENTOUT. |
| 60 | BOOT0 | input | Dedicated boot-mode select input, together with BOOT1, sampled at reset to choose booting from user Flash, system memory or embedded SRAM; input voltage range 0-9 V and also used as the VPP high-voltage programming pin (min. 7 V, max 9 V, min. 10 mA sink). |
| 61 | PB8 | bidirectional | 5V-tolerant I/O usable as I2C1_SCL, TIM4_CH3, TIM10_CH1, SDIO_D4, or EVENTOUT. |
| 62 | PB9 | bidirectional | 5V-tolerant I/O usable as SPI2_NSS/I2S2_WS, I2C1_SDA, TIM4_CH4, TIM11_CH1, SDIO_D5, or EVENTOUT. |
| 63 | VSS | power_in | Digital ground supply pin. |
| 64 | VDD | power_in | Digital power supply pin, standard operating voltage 1.7-3.6 V (1.8-3.6 V with the internal regulator enabled). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
STM32F401RCT6 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
stm32f401rct6-etched.step/stm32f401rct6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f401rct6.step/stm32f401rct6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (139 pp, sha256
ea0100f21bbbb0da, retrieved 2026-09-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).