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README

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TPS70748PWP

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-20-EP

TPS70748PWP from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connection; the pin is not connected internally and may be left open.
2 VIN1 power_in Input voltage of regulator 1; internal bias voltages are powered from VIN1, and the UVLO circuit keeps regulator 1 off until VIN1 reaches 2.5 V.
3 VIN1 power_in Input voltage of regulator 1; internal bias voltages are powered from VIN1, and the UVLO circuit keeps regulator 1 off until VIN1 reaches 2.5 V.
4 MR1 input Manual reset input 1, active low, with an internal 6-µA pull-up to VIN1; a logic low triggers a POR (RESET).
5 MR2 input Manual reset input 2, active low, with an internal 6-µA pull-up to VIN1; a logic low triggers a POR (RESET).
6 EN input Active-low enable: the device is enabled when EN is at a low level and is put into sleep mode (about 1 µA input current at TJ = +25°C) when EN is driven high.
7 SEQ input Power-up sequence control: high or open turns VOUT2 on first, low turns VOUT1 on first; the pin has an internal 6-µA pull-up to VIN1.
8 GND power_in Ground reference for the device.
9 VIN2 power_in Input voltage of regulator 2.
10 VIN2 power_in Input voltage of regulator 2.
11 NC unconnected No connection; the pin is not connected internally and may be left open.
12 VOUT2 power_out Output voltage of regulator 2, rated for up to 125 mA.
13 VOUT2 power_out Output voltage of regulator 2, rated for up to 125 mA.
14 VSENSE2/FB2 input Regulator 2 output voltage sense on fixed versions (connect to VOUT2 as close as possible) or feedback input on the adjustable version, to be tied to the external resistor divider.
15 RESET output Open-drain, active-low power-on reset output that goes low when VOUT2 is below 95% of its regulated voltage or a manual reset input is low, and needs a pull-up resistor.
16 PG1 output Open-drain power-good output that is low when VOUT1 is below 95% of its regulated voltage and needs a pull-up resistor.
17 VSENSE1/FB1 input Regulator 1 output voltage sense on fixed versions (connect to VOUT1 as close as possible) or feedback input on the adjustable version, to be tied to the external resistor divider.
18 VOUT1 power_out Output voltage of regulator 1, rated for up to 250 mA.
19 VOUT1 power_out Output voltage of regulator 1, rated for up to 250 mA.
20 NC unconnected No connection; the pin is not connected internally and may be left open.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-20-EP
Category Power Management (PMIC)
Pins 21

CAD (KiCad official)

  • Symbol: TPS70748PWP
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps70748pwp-etched.step / tps70748pwp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps70748pwp.step / tps70748pwp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 47c201c539729fd2, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF