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LMX2430TMX

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Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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LMX2430TMX

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-20

LMX2430TMX from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Power supply bias for the RF PLL analog circuits; Vcc may range from 2.25 V to 2.75 V, and bypass capacitors must be placed as close as possible to this pin and connected directly to the ground plane.
2 GND power_in Ground for the IF PLL analog and digital circuits, MICROWIRE, Ftest/LD and oscillator circuits.
3 FinIF input IF PLL prescaler input, a small-signal input from the VCO.
4 EN input Chip enable: HIGH powers up the RF and IF PLLs with power-down then controlled through MICROWIRE; LOW asynchronously powers down the device and forces the charge-pump outputs to a high-impedance (tri-state) state.
5 CPoutIF output IF PLL charge-pump output, connected to the external loop filter that drives the input of the IF VCO.
6 ENosc input Oscillator enable: HIGH keeps the oscillator buffer powered up independent of EN; LOW configures OSCout/FLoutIF as the IF fastlock output.
7 OSCout/FLoutIF output Oscillator output for an external crystal when ENosc is HIGH, or IF PLL fastlock output (also a general-purpose CMOS tri-state output) when ENosc is LOW, connecting a resistor in parallel to R2 of the external loop filter.
8 OSCin input Reference oscillator input with an approximate Vcc/2 threshold, driven by an external AC-coupled source.
9 VCC power_in Power supply bias for the RF PLL analog circuits; Vcc may range from 2.25 V to 2.75 V, and bypass capacitors must be placed as close as possible to this pin and connected directly to the ground plane.
10 Ftest/LD output Programmable multiplexed output that functions as a general-purpose CMOS tri-state output, N and R divider output, RF/IF PLL push-pull or open-drain analog lock-detect output, or RF/IF PLL digital filtered lock-detect output.
11 FLoutRF output RF PLL fastlock output connecting a resistor in parallel to R2 of the external loop filter, which can also function as a general-purpose CMOS tri-state output.
12 GND power_in Ground for the IF PLL analog and digital circuits, MICROWIRE, Ftest/LD and oscillator circuits.
13 CPoutRF output RF PLL charge-pump output, connected to the external loop filter that drives the input of the RF VCO.
14 GND power_in Ground for the IF PLL analog and digital circuits, MICROWIRE, Ftest/LD and oscillator circuits.
15 FinRF input RF PLL prescaler input, a small-signal input from the VCO.
16 FinRF* input RF PLL prescaler complementary input; for single-ended operation it must be AC grounded through a 100-pF capacitor, and the device can be driven differentially when that AC-coupling capacitor is omitted.
17 VCC power_in Power supply bias for the RF PLL analog circuits; Vcc may range from 2.25 V to 2.75 V, and bypass capacitors must be placed as close as possible to this pin and connected directly to the ground plane.
18 LE input MICROWIRE latch enable, high-impedance CMOS input; when LE transitions HIGH, data in the shift register is loaded into one of 6 internal control registers.
19 CLK input MICROWIRE clock input, high-impedance CMOS; DATA is clocked into the 24-bit shift register on the rising edge of CLK.
20 DATA input MICROWIRE data input, high-impedance CMOS; binary serial data with the MSB shifted in first and the two last bits being the control bits.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Clock/Timing
Pins 20

CAD (KiCad official)

  • Symbol: LMX2430TMX
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: lmx2430tmx-etched.step / lmx2430tmx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmx2430tmx.step / lmx2430tmx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (56 pp, sha256 e729234c7e638f2b, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF