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EFM8LB12F32E-C-QFP32

Public Made by Adom

by adom

SILICON LABS Pre-ordered MCUs, VQFN-32-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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EFM8LB12F32E-C-QFP32

SILICON LABS · Pre-ordered MCUs · VQFN-32-EP(4x4)

EFM8LB12F32E-C-QFP32 from SILICON LABS, in a VQFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0.0 bidirectional Multifunction I/O pin with crossbar capability that also carries the VREF analog function.
2 GND power_in Ground supply pin.
3 VIO power_in I/O supply power input from which the external port I/O pins are powered.
4 VDD power_in Supply power input for internal circuitry; device operation is specified from 2.2 V up to 3.6 V.
5 RSTb / C2CK input Active-low reset input that doubles as the C2 debug clock.
6 P3.7 / C2D bidirectional Multifunction I/O pin that is also the C2 debug data signal.
7 P3.3 bidirectional Multifunction I/O pin with DAC3 analog output function.
8 P3.2 bidirectional Multifunction I/O pin with DAC2 analog output function.
9 P3.1 bidirectional Multifunction I/O pin with DAC1 analog output function.
10 P3.0 bidirectional Multifunction I/O pin with DAC0 analog output function.
11 P2.6 bidirectional Multifunction I/O pin with ADC0 input 19 and comparator 1 inputs.
12 P2.5 bidirectional Multifunction I/O pin with CLU3 output and ADC0 input 18.
13 P2.4 bidirectional Multifunction I/O pin with ADC0 input 17 and comparator 1 inputs.
14 P2.3 bidirectional Crossbar-capable multifunction I/O pin with ADC0 input 16 and comparator 1 inputs.
15 P2.2 bidirectional Crossbar-capable multifunction I/O pin with CLU2 output and ADC0 input 15.
16 P2.1 bidirectional Crossbar-capable multifunction I/O pin with I2C0 SCL and ADC0 input 14.
17 P2.0 bidirectional Crossbar-capable multifunction I/O pin with I2C0 SDA and comparator 1 inputs.
18 P1.7 bidirectional Crossbar-capable multifunction I/O pin with ADC0 input 13 and comparator 0 inputs.
19 P1.6 bidirectional Crossbar-capable multifunction I/O pin with ADC0 input 12.
20 P1.5 bidirectional Crossbar-capable multifunction I/O pin with ADC0 input 11.
21 P1.4 bidirectional Crossbar-capable multifunction I/O pin with ADC0 input 10.
22 P1.3 bidirectional Crossbar-capable multifunction I/O pin with ADC0 input 9.
23 P1.2 bidirectional Crossbar-capable multifunction I/O pin with ADC0 input 8 and comparator 0 inputs.
24 P1.1 bidirectional Crossbar-capable multifunction I/O pin with ADC0 input 7 and comparator 0 inputs.
25 P1.0 bidirectional Crossbar-capable multifunction I/O pin with ADC0 input 6 and comparator 0 and comparator 1 inputs.
26 P0.7 bidirectional Crossbar-capable multifunction I/O pin with INT0.7/INT1.7, ADC0 input 5 and comparator inputs.
27 P0.6 bidirectional Crossbar-capable multifunction I/O pin that also serves as the CNVSTR ADC conversion start input, with ADC0 input 4.
28 P0.5 bidirectional Crossbar-capable multifunction I/O pin that carries the UART0 RX function and ADC0 input 3.
29 P0.4 bidirectional Crossbar-capable multifunction I/O pin that carries the UART0 TX function and ADC0 input 2.
30 P0.3 bidirectional Crossbar-capable multifunction I/O pin that also serves as the EXTCLK external clock input and EXTOSC oscillator function.
31 P0.2 bidirectional Crossbar-capable multifunction I/O pin with ADC0 input 1 and comparator 0 inputs.
32 P0.1 bidirectional Crossbar-capable multifunction I/O pin with ADC0 input 0 and comparator 0 inputs.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package VQFN-32-EP(4x4)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Supply Voltage on VDD VDD 2.2 3.6 V 18
Operating Supply Voltage on VIO VIO 2.2 V 18
Operating Supply Voltage on VIO (reduced range) VIO 1.713 V 18
System Clock Frequency fSYSCLK 0 73.5 MHz 18
Operating Ambient Temperature TA -40 105 °C 18
Digital Core Supply Current, Normal mode IDD 12.9 15 mA Normal Mode, code executing from flash; FSYSCLK = 72 MHz (HFOSC1) 19
Digital Core Supply Current, Normal mode IDD 4.2 5 mA Normal Mode, code executing from flash; FSYSCLK = 24.5 MHz (HFOSC0) 19
Digital Core Supply Current, Normal mode IDD 625 1050 μA Normal Mode, code executing from flash; FSYSCLK = 1.53 MHz (HFOSC0) 19
Digital Core Supply Current, Normal mode IDD 155 575 μA Normal Mode, code executing from flash; FSYSCLK = 80 kHz 19
Digital Core Supply Current, Idle mode IDD 9.6 11.1 mA Idle Mode, core halted with peripherals running; FSYSCLK = 72 MHz (HFOSC1) 19
Digital Core Supply Current, Idle mode IDD 3.14 3.8 mA Idle Mode, core halted with peripherals running; FSYSCLK = 24.5 MHz (HFOSC0) 19
Digital Core Supply Current, Idle mode IDD 520 950 μA Idle Mode, core halted with peripherals running; FSYSCLK = 1.53 MHz (HFOSC0) 19
Digital Core Supply Current, Idle mode IDD 135 550 μA Idle Mode, core halted with peripherals running; FSYSCLK = 80 kHz 19
Digital Core Supply Current, Suspend mode IDD 125 545 μA Suspend Mode, core halted, high frequency clocks stopped, supply monitor off; LFO Running 19
Digital Core Supply Current, Suspend mode IDD 120 535 μA Suspend Mode, core halted, high frequency clocks stopped, supply monitor off; LFO Stopped 19
Digital Core Supply Current, Snooze mode IDD 23 430 μA Snooze Mode, core halted, high frequency clocks stopped, regulator low-power, supply monitor off; LFO Running 19
Digital Core Supply Current, Snooze mode IDD 19 425 μA Snooze Mode, core halted, high frequency clocks stopped, regulator low-power, supply monitor off; LFO Stopped 19
Digital Core Supply Current, Stop mode IDD 120 535 μA Stop Mode, core halted and all clocks stopped, internal LDO on, supply monitor off 19
Digital Core Supply Current, Shutdown mode IDD 0.2 2.1 μA Shutdown Mode, core halted and all clocks stopped, internal LDO off, supply monitor off 19
High-Frequency Oscillator 0 Supply Current IHFOSC0 120 135 μA Operating at 24.5 MHz, TA = 25 °C 19
High-Frequency Oscillator 1 Supply Current IHFOSC1 1285 1340 μA Operating at 72 MHz, TA = 25 °C 19
Low-Frequency Oscillator Supply Current ILFOSC 3.7 6 μA Operating at 80 kHz, TA = 25 °C 19
Throughput Rate (High Speed Mode) fS 900 ksps 14 Bit Mode 24
Throughput Rate (High Speed Mode) fS 1 Msps 12 Bit Mode 24
Throughput Rate (High Speed Mode) fS 1.125 Msps 10 Bit Mode 24
Tracking Time (High Speed Mode) tTRK 217.81 ns High Speed Mode 24
Tracking Time (Low Power Mode) tTRK 450 ns Low Power Mode 24
SAR Clock Frequency (High Speed Mode) fSAR 18.36 MHz High Speed Mode 24
Integral Nonlinearity 14 Bit Mode INL -3.54 8.54 LSB 14 Bit Mode 25
Integral Nonlinearity 12 Bit Mode INL -1.9 1.9 LSB 12 Bit Mode 25
Integral Nonlinearity 10 Bit Mode INL -0.6 0.6 LSB 10 Bit Mode 25
Differential Nonlinearity (Guaranteed Monotonic) 14 Bit Mode DNL -14 2.54 LSB 14 Bit Mode 25
Differential Nonlinearity (Guaranteed Monotonic) 12 Bit Mode DNL -0.9 0.9 LSB 12 Bit Mode 25
Differential Nonlinearity (Guaranteed Monotonic) 10 Bit Mode DNL -0.5 0.5 LSB 10 Bit Mode 25
Offset Error 14 Bit Mode EOFF -84 -2.5 8 LSB 14 Bit Mode 25
Offset Error 12 Bit Mode EOFF -2 0 2 LSB 12 Bit Mode 25
Offset Error 10 Bit Mode EOFF -1 0 1 LSB 10 Bit Mode 25
Internal Fast Settling Reference Output Voltage (Full Temperature and Supply Range) VREFFS 1.62 1.65 1.68 V Full Temperature and Supply Range 27
Internal Fast Settling Reference Turn-on Time tREFFS 1.5 μs 27
Valid Supply Range, 1.2 V Output VDD 2.2 3.6 V 1.2 V Output 27
Valid Supply Range, 2.4 V Output VDD 2.7 3.6 V 2.4 V Output 27
On-chip Precision Reference Output Voltage VREFP 1.195 1.2 1.205 V 1.2 V Output, VDD = 3.3 V, T = 25 °C 27
On-chip Precision Reference Output Voltage VREFP 1.18 1.2 1.22 V 1.2 V Output 27
On-chip Precision Reference Output Voltage VREFP 2.39 2.4 2.41 V 2.4 V Output, VDD = 3.3 V, T = 25 °C 27
On-chip Precision Reference Output Voltage VREFP 2.36 2.4 2.44 V 2.4 V Output 27
Temp Sensor Error Using Typical Slope and Factory-Calibrated Offset ETOT -2.6 1.8 °C T = 0 °C to 70 °C 28
Temp Sensor Error Using Typical Slope and Factory-Calibrated Offset ETOT -2.9 2.7 °C T = -20 °C to 85 °C 28
Temp Sensor Error Using Typical Slope and Factory-Calibrated Offset ETOT -3.2 4.2 °C T = -40 °C to 105 °C 28
Output Voltage, 1.8 V Internal LDO Regulator VOUT_1.8V 1.79 1.84 1.88 V 28
Operating Junction Temperature TJ -40 130 °C TA = -40 °C to 105 °C 36
Ambient Temperature Under Bias TBIAS -55 125 °C 36
Storage Temperature TSTG -65 150 °C 36
Voltage on VDD VDD 4.2 V 36
Voltage on I/O pins or RSTb, excluding P3.0-P3.3 (QFN32 and QFP32) VIN 5.8 V VIO > 3.3 V 36
Total Current Sunk into Supply Pin IVDD 400 mA 36
Total Current Sourced out of Ground Pin IGND 400 mA 36
Current Sourced or Sunk by any I/O Pin or RSTb IIO -100 100 mA 36
Thermal Resistance (Junction to Ambient), QFP32 Packages θJA 80 °C/W QFP32 Packages; multi-layer PCB 35
Thermal Resistance (Junction to Case), QFP32 Packages θJC 24.3 °C/W QFP32 Packages 35

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 60

CAD (KiCad official)

  • Symbol: EFM8LB12F32E-C-QFP32
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: VQFN-32-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: efm8lb12f32e-c-qfp32-etched.step / efm8lb12f32e-c-qfp32-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efm8lb12f32e-c-qfp32.step / efm8lb12f32e-c-qfp32.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (77 pp, sha256 4bb882f3cda45564, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF