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SN74ALVC10PWR
Public Made by Adomby adom
Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74ALVC10PWR
Texas Instruments · Logic Gates · TSSOP-14
SN74ALVC10PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input A of NAND gate 1; input voltage range is 0 V to 3.6 V and unused inputs must be held at VCC or GND. |
| 2 | 1B | input | Input B of NAND gate 1; input voltage range is 0 V to 3.6 V and unused inputs must be held at VCC or GND. |
| 3 | 2A | input | Input A of NAND gate 2; input voltage range is 0 V to 3.6 V and unused inputs must be held at VCC or GND. |
| 4 | 2B | input | Input B of NAND gate 2; input voltage range is 0 V to 3.6 V and unused inputs must be held at VCC or GND. |
| 5 | 2C | input | Input C of NAND gate 2; input voltage range is 0 V to 3.6 V and unused inputs must be held at VCC or GND. |
| 6 | 2Y | output | Output of NAND gate 2 (Y = A·B·C inverted); at VCC = 3 V the datasheet specifies IOH of -24 mA and IOL of 24 mA. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 3Y | output | Output of NAND gate 3 (Y = A·B·C inverted); at VCC = 3 V the datasheet specifies IOH of -24 mA and IOL of 24 mA. |
| 9 | 3A | input | Input A of NAND gate 3; input voltage range is 0 V to 3.6 V and unused inputs must be held at VCC or GND. |
| 10 | 3B | input | Input B of NAND gate 3; input voltage range is 0 V to 3.6 V and unused inputs must be held at VCC or GND. |
| 11 | 3C | input | Input C of NAND gate 3; input voltage range is 0 V to 3.6 V and unused inputs must be held at VCC or GND. |
| 12 | 1Y | output | Output of NAND gate 1 (Y = A·B·C inverted); at VCC = 3 V the datasheet specifies IOH of -24 mA and IOL of 24 mA. |
| 13 | 1C | input | Input C of NAND gate 1; input voltage range is 0 V to 3.6 V and unused inputs must be held at VCC or GND. |
| 14 | VCC | power_in | Supply voltage, 1.65 V to 3.6 V recommended operating range. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74ALVC10PWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74alvc10pwr-etched.step/sn74alvc10pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74alvc10pwr.step/sn74alvc10pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (18 pp, sha256
eb201f209133d97e, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).