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MSP430G2233IPW20R
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430G2233IPW20R
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TSSOP-20
MSP430G2233IPW20R from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DVCC | power_in | Digital supply voltage, 1.8 V to 3.6 V during program execution (VCC supply range). |
| 2 | P1.0/TA0CLK/ACLK/A0 | bidirectional | General-purpose digital I/O pin, also Timer0_A clock input, ACLK output and ADC10 analog input A0 (G2x33 only). |
| 3 | P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1 | bidirectional | General-purpose digital I/O pin, also Timer0_A capture/compare, USCI_A0 UART receive or SPI slave out, and ADC10 analog input A1 (G2x33 only). |
| 4 | P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2 | bidirectional | General-purpose digital I/O pin, also Timer0_A compare Out1, USCI_A0 UART transmit or SPI slave in, and ADC10 analog input A2 (G2x33 only). |
| 5 | P1.3/ADC10CLK/A3/VREF-/VEREF- | bidirectional | General-purpose digital I/O pin, also ADC10 conversion clock output, analog input A3 and negative reference voltage (G2x33 only). |
| 6 | P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/TCK | bidirectional | General-purpose digital I/O pin, also SMCLK output, USCI slave transmit enable or clock, ADC10 positive reference and analog input A4 (G2x33 only), and JTAG test clock input TCK. |
| 7 | P1.5/TA0.0/UCB0CLK/UCA0STE/A5/TMS | bidirectional | General-purpose digital I/O pin, also Timer0_A compare Out0, USCI clock or slave transmit enable, ADC10 analog input A5 (G2x33 only), and JTAG test mode select TMS. |
| 8 | P2.0/TA1.0 | bidirectional | General-purpose digital I/O pin, also Timer1_A capture CCI0A input or compare Out0 output. |
| 9 | P2.1/TA1.1 | bidirectional | General-purpose digital I/O pin, also Timer1_A capture CCI1A input or compare Out1 output. |
| 10 | P2.2/TA1.1 | bidirectional | General-purpose digital I/O pin, also Timer1_A capture CCI1B input or compare Out1 output. |
| 11 | P2.3/TA1.0 | bidirectional | General-purpose digital I/O pin, also Timer1_A capture CCI0B input or compare Out0 output. |
| 12 | P2.4/TA1.2 | bidirectional | General-purpose digital I/O pin, also Timer1_A capture CCI2A input or compare Out2 output. |
| 13 | P2.5/TA1.2 | bidirectional | General-purpose digital I/O pin, also Timer1_A capture CCI2B input or compare Out2 output. |
| 14 | P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/TDI/TCLK | bidirectional | General-purpose digital I/O pin, also Timer0_A compare Out1, USCI_B0 SPI slave out or I2C clock, ADC10 analog input A6 (G2x33 only), and JTAG test data input TDI/TCLK. |
| 15 | P1.7/UCB0SIMO/UCB0SDA/A7/TDO/TDI | bidirectional | General-purpose digital I/O pin, also USCI_B0 SPI slave in or I2C data, ADC10 analog input A7 (G2x33 only), and JTAG test data output TDO or input TDI. |
| 16 | RST/NMI/SBWTDIO | input | Device reset input, also nonmaskable interrupt input and Spy-Bi-Wire test data input/output during programming and test. |
| 17 | TEST/SBWTCK | input | Selects test mode for the JTAG pins on Port 1, and is the Spy-Bi-Wire test clock input during programming and test; the device protection fuse is connected to TEST. |
| 18 | XOUT/P2.7 | bidirectional | Output terminal of the crystal oscillator, also general-purpose digital I/O P2.7; if used as an input, excess current flows until P2SEL.7 is cleared. |
| 19 | XIN/P2.6/TA0.1 | bidirectional | Input terminal of the crystal oscillator, also general-purpose digital I/O P2.6 and Timer0_A compare Out1. |
| 20 | DVSS | power_in | Ground reference for the digital supply. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Embedded Processors & Controllers |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage during program execution | VCC | 1.8 | 3.6 | V | During program execution | 13 | |
| Supply voltage during flash programming or erase | VCC | 2.2 | 3.6 | V | During flash programming or erase | 13 | |
| Operating free-air temperature | TA | -40 | 85 | °C | 13 | ||
| Processor frequency (maximum MCLK frequency using the USART module) | fSYSTEM | 6 | MHz | VCC = 1.8 V, Duty cycle = 50% ±10% | 13 | ||
| Processor frequency (maximum MCLK frequency using the USART module) | fSYSTEM | 12 | MHz | VCC = 2.7 V, Duty cycle = 50% ±10% | 13 | ||
| Processor frequency (maximum MCLK frequency using the USART module) | fSYSTEM | 16 | MHz | VCC = 3.3 V, Duty cycle = 50% ±10% | 13 | ||
| Voltage applied at VCC to VSS | -0.3 | 4.1 | V | 13 | |||
| Voltage applied to any pin | -0.3 | V | Max printed as VCC + 0.3 V | 13 | |||
| Diode current at any device pin | -2 | 2 | mA | 13 | |||
| Storage temperature, unprogrammed device | Tstg | -55 | 150 | °C | Unprogrammed device | 13 | |
| Storage temperature, programmed device | Tstg | -55 | 150 | °C | Programmed device | 13 | |
| Electrostatic discharge, human-body model | V(ESD) | -1000 | 1000 | V | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 | 13 | |
| Electrostatic discharge, charged-device model | V(ESD) | -250 | 250 | V | Charged-device model (CDM), per JEDEC JESD22-C101 | 13 | |
| Schmitt-trigger positive-going input threshold voltage (general) | VIT+ | 0.45 | 0.75 | V | Printed as 0.45 VCC to 0.75 VCC | 19 | |
| Schmitt-trigger positive-going input threshold voltage | VIT+ | 1.35 | 2.25 | V | VCC = 3 V | 19 | |
| Schmitt-trigger negative-going input threshold voltage (general) | VIT- | 0.25 | 0.55 | V | Printed as 0.25 VCC to 0.55 VCC | 19 | |
| Schmitt-trigger negative-going input threshold voltage | VIT- | 0.75 | 1.65 | V | VCC = 3 V | 19 | |
| Input voltage hysteresis (VIT+, VIT-) | Vhys | 0.3 | 1 | V | VCC = 3 V | 19 | |
| Pullup or pulldown resistor | RPull | 20 | 35 | 50 | kΩ | VCC = 3 V; for pullup: VIN = VSS, for pulldown: VIN = VCC | 19 |
| High-impedance leakage current | Ilkg(Px.y) | -50 | 50 | nA | VCC = 3 V; See (1)(2) | 19 | |
| Port output frequency (with load) | fPx.y | 12 | MHz | Px.y, CL = 20 pF, RL = 1 kΩ; VCC = 3 V | 19 | ||
| Clock output frequency | fPort_CLK | 16 | MHz | Px.y, CL = 20 pF; VCC = 3 V | 19 | ||
| DCO frequency (15, 7) | fDCO(15,7) | 16 | 26 | MHz | RSELx = 15, DCOx = 7, MODx = 0; VCC = 3 V | 24 | |
| DCO frequency (0, 0) | fDCO(0,0) | 0.06 | 0.14 | MHz | RSELx = 0, DCOx = 0, MODx = 0; VCC = 3 V | 24 | |
| DCO frequency (15, 3) | fDCO(15,3) | 12 | 18.5 | MHz | RSELx = 15, DCOx = 3, MODx = 0; VCC = 3 V | 24 | |
| 1-MHz tolerance over temperature | -3 | 3 | % | BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30°C and 3 V; 0°C to 85°C, 3 V | 25 | ||
| 1-MHz tolerance overall | -6 | 6 | % | BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30°C and 3 V; -40°C to 85°C, 1.8 V to 3.6 V | 25 | ||
| 8-MHz tolerance overall | -6 | 6 | % | BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30°C and 3 V; -40°C to 85°C, 2.2 V to 3.6 V | 25 | ||
| 16-MHz tolerance overall | -6 | 6 | % | BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30°C and 3 V; -40°C to 85°C, 3.3 V to 3.6 V | 25 | ||
| LFXT1 oscillator logic level square-wave input frequency, LF mode | fLFXT1,LF,logic | 10000 | 32768 | 50000 | Hz | XTS = 0, XCAPx = 0, LFXT1Sx = 3; 1.8 V to 3.6 V | 27 |
| Duty cycle, LF mode | 30 | 50 | 70 | % | XTS = 0, measured at P2.0/ACLK, fLFXT1,LF = 32768 Hz; 2.2 V | 27 | |
| Oscillator fault frequency, LF mode | fFault,LF | 10 | 10000 | Hz | XTS = 0, XCAPx = 0, LFXT1Sx = 3; 2.2 V | 27 | |
| VLO frequency | fVLO | 4 | 12 | 20 | kHz | -40°C to 85°C; 3 V | 27 |
| Low-power mode 3 current (LPM3) with LFXT1 | ILPM3,LFXT1 | 0.7 | 1.5 | µA | TA = 25°C, VCC = 2.2 V, fACLK = 32768 Hz | 16 | |
| Low-power mode 3 current (LPM3) with VLO | ILPM3,VLO | 0.5 | 0.7 | µA | TA = 25°C, VCC = 2.2 V, fACLK from internal LF oscillator (VLO) | 16 | |
| Low-power mode 4 current (LPM4) | ILPM4 | 0.1 | 0.5 | µA | TA = 25°C, VCC = 2.2 V, fACLK = 0 Hz, OSCOFF = 1 | 16 | |
| Low-power mode 4 current (LPM4) | ILPM4 | 0.8 | 1.7 | µA | TA = 85°C, VCC = 2.2 V, fACLK = 0 Hz, OSCOFF = 1 | 16 | |
| Active mode (AM) current at 1 MHz | IAM,1MHz | 330 | 420 | µA | VCC = 3 V; fDCO = fMCLK = fSMCLK = 1 MHz, fACLK = 0 Hz, program executes in flash | 14 | |
| Analog supply voltage | VCC | 2.2 | 3.6 | V | VSS = 0 V | 31 | |
| Positive built-in reference voltage | VREF+ | 1.41 | 1.5 | 1.59 | V | IVREF+ ≤ IVREF+max, REF2_5V = 0; VCC = 3 V | 32 |
| Positive built-in reference voltage | VREF+ | 2.35 | 2.5 | 2.65 | V | IVREF+ ≤ IVREF+max, REF2_5V = 1; VCC = 3 V | 32 |
| Temperature coefficient of built-in reference | TCREF+ | -100 | 100 | ppm/°C | IVREF+ = const with 0 mA ≤ IVREF+ ≤ 1 mA; 3 V | 32 | |
| ADC10 input clock frequency (ADC10SR = 0) | fADC10CLK | 0.45 | 6.3 | MHz | For specified performance of ADC10 linearity parameters; ADC10SR = 0; 3 V | 32 | |
| ADC10 input clock frequency (ADC10SR = 1) | fADC10CLK | 0.45 | 1.5 | MHz | For specified performance of ADC10 linearity parameters; ADC10SR = 1; 3 V | 32 | |
| ADC10 built-in oscillator frequency | fADC10OSC | 3.7 | 6.3 | MHz | ADC10DIVx = 0, ADC10SSELx = 0, fADC10CLK = fADC10OSC; 3 V | 32 | |
| Conversion time | tCONVERT | 2.06 | 3.51 | µs | ADC10 built-in oscillator, ADC10SSELx = 0, fADC10CLK = fADC10OSC; 3 V | 32 | |
| Integral linearity error | EI | -1 | 1 | LSB | 3 V | 33 | |
| Differential linearity error | ED | -1 | 1 | LSB | 3 V | 33 | |
| Gain error | EG | -2 | 2 | LSB | 3 V | 33 | |
| Total unadjusted error | ET | -5 | 5 | LSB | 3 V | 33 | |
| Low-power mode 0 current (LPM0) | ILPM0,1MHz | 56 | µA | TA = 25°C, VCC = 2.2 V, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz | 16 | ||
| Low-power mode 2 current (LPM2) | ILPM2 | 22 | µA | TA = 25°C, VCC = 2.2 V, fMCLK = fSMCLK = 0 MHz, fDCO = 1 MHz | 16 | ||
| Active mode (AM) current at 1 MHz | IAM,1MHz | 230 | µA | VCC = 2.2 V; fDCO = fMCLK = fSMCLK = 1 MHz, fACLK = 0 Hz, program executes in flash | 14 | ||
| Input capacitance | CI | 5 | pF | VIN = VSS or VCC | 19 | ||
| Junction-to-ambient thermal resistance, still air | RθJA | 86.5 | °C/W | TSSOP (PW-20) | 18 | ||
| Junction-to-case (top) thermal resistance | RθJC(TOP) | 20.8 | °C/W | TSSOP (PW-20) | 18 | ||
| Junction-to-board thermal resistance | θJB | 39 | °C/W | TSSOP (PW-20) | 18 | ||
| Junction-to-package-top characterization parameter | ΨJT | 0.8 | °C/W | TSSOP (PW-20) | 18 | ||
| Junction-to-board characterization parameter | ΨJB | 38.1 | °C/W | TSSOP (PW-20) | 18 |
CAD (KiCad official)
- Symbol:
MSP430G2233IPW20R - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
msp430g2233ipw20r-etched.step/msp430g2233ipw20r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430g2233ipw20r.step/msp430g2233ipw20r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (96 pp, sha256
37b72756d9da8e02, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).