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BQ24160ARGER

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Texas Instruments Battery Management, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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BQ24160ARGER

Texas Instruments · Battery Management · VQFN-24-EP(4x4)

BQ24160ARGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D- input D+ and D- are USB input adapter detection connections; a short between D+ and D- sets the USB input current limit to 1.5 A, otherwise the USB100 mode is selected.
2 D+ input D+ and D- are USB input adapter detection connections; a short between D+ and D- sets the USB input current limit to 1.5 A, and the D+/D- detection has no effect on the IN input.
3 SCL input I2C interface clock; connect SCL to the logic rail through a 10-kΩ resistor.
4 SDA bidirectional I2C interface data; connect SDA to the logic rail through a 10-kΩ resistor.
5 PGND power_in Ground terminal; connect to the thermal pad (VQFN only) and the ground plane of the circuit.
6 DRV power_out Bias supply for the gate drive of the internal MOSFETs; bypass DRV to PGND with a 1-µF ceramic capacitor, and DRV may drive external loads up to 10 mA.
7 INT output Open-drain status output that pulls low during charging and sends a 128-µs interrupt pulse on a fault; connect INT to a logic rail through a 100-kΩ resistor.
8 STAT output Open-drain status output that pulls low during charging and sends a 128-µs interrupt pulse on a fault; pull up through an LED for indication or a 10-kΩ resistor to communicate with the host, with a sink current limit of 10 mA.
9 TS input Battery pack NTC monitor input; connect to the center tap of a resistor divider from DRV to GND with the NTC from TS to GND, and connect TS to DRV to disable the TS function.
10 BGATE output Gate drive output for an external P-channel discharge MOSFET, low during high-impedance mode and when no input is connected.
11 BAT bidirectional Battery connection to the positive terminal of the battery; bypass BAT to GND with at least a 1-µF capacitor.
12 BAT bidirectional Battery connection to the positive terminal of the battery; bypass BAT to GND with at least a 1-µF capacitor.
13 SYS input System voltage sense and charger FET connection; connect to the system output at the bulk capacitors and bypass locally with at least 10 µF (47 µF recommended for optimal transient response).
14 SYS input System voltage sense and charger FET connection; connect to the system output at the bulk capacitors and bypass locally with at least 10 µF (47 µF recommended for optimal transient response).
15 PGND power_in Ground terminal; connect to the thermal pad (VQFN only) and the ground plane of the circuit.
16 PGND power_in Ground terminal; connect to the thermal pad (VQFN only) and the ground plane of the circuit.
17 PGND power_in Ground terminal; connect to the thermal pad (VQFN only) and the ground plane of the circuit.
18 SW output Inductor connection; connect to the switched side of the external inductor.
19 BOOT input High-side MOSFET gate driver supply; connect a 0.01-µF ceramic capacitor (voltage rating > 10 V) from BOOT to SW.
20 PMIDI output Reverse blocking MOSFET and high-side MOSFET connection point for the high-power input; bypass with at least 4.7 µF to GND, and the output is not current limited so any short will damage the IC.
21 IN input Input power supply connected to the external DC supply (AC adapter or alternate power source); bypass to PGND with at least a 1-µF ceramic capacitor.
22 USB input USB input power supply connected to the external DC supply (AC adapter or USB port); bypass to PGND with at least a 1-µF ceramic capacitor.
23 PMIDU output Reverse blocking MOSFET and high-side MOSFET connection point for the USB input; bypass with at least 4.7 µF to GND, and the output is not current limited so any short will damage the IC.
24 CD input IC hardware chip disable input; drive CD high to place the device in high-Z mode and low for normal operation, and do not leave CD unconnected.
25 PGND passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Power Management (PMIC)
Pins 25

CAD (KiCad official)

  • Symbol: BQ24160ARGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: bq24160arger-etched.step / bq24160arger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq24160arger.step / bq24160arger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (55 pp, sha256 701c8b87e51cde27, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF