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EA3056QDR

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by adom

Everanalog IC design DC-DC Converters, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)ea3056qdrfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

Schematic Symbol

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Datasheet

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Contents

README

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EA3056QDR

Everanalog IC design · DC-DC Converters · QFN-24-EP(4x4)

EA3056QDR from Everanalog IC design, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LDO_G power_in Ground pin of the LDO.
2 LDO_FB input Feedback input of the LDO; connect to LDO_O with a resistor divider.
3 VCC power_in Input supply pin for the internal control circuit; recommended range 2.7V to 5.5V.
4 AGND power_in Analog ground pin.
5 FB2 input Feedback input of CH2; connect to the output voltage with a resistor divider.
6 PGND2 power_in Power ground pin of CH2.
7 LX2 output Internal MOSFET switching output of CH2; connect to a low-pass filter (inductor and output capacitor) to obtain a stable DC output.
8 VIN2 power_in Power input pin of CH2; recommended 4.7uF MLCC between VIN2 and PGND2. Input range 2.7V to 5.5V.
9 EN2 input CH2 on/off control input; must not be left floating.
10 EN1 input CH1 on/off control input; must not be left floating.
11 VIN1 power_in Power input pin of CH1; recommended two 10uF MLCC capacitors between VIN1 and PGND1. Input range 2.7V to 5.5V.
12 LX1 output Internal MOSFET switching output of CH1; connect to a low-pass filter (inductor and output capacitor) to obtain a stable DC output.
13 PGND1 power_in Power ground pin of CH1.
14 FB1 input Feedback input of CH1; connect to the output voltage with a resistor divider.
15 SDA bidirectional I2C interface data pin.
16 SCL input I2C interface clock pin.
17 FB3 input Feedback input of CH3; connect to the output voltage with a resistor divider.
18 PGND3 power_in Power ground pin of CH3.
19 LX3 output Internal MOSFET switching output of CH3; connect to a low-pass filter (inductor and output capacitor) to obtain a stable DC output.
20 VIN3 power_in Power input pin of CH3; recommended 10uF MLCC between VIN3 and PGND3. Input range 2.7V to 5.5V.
21 EN3 input CH3 on/off control input (the datasheet pin description says CH4, which appears to be a typo); must not be left floating.
22 LDO_EN input LDO on/off control input; must not be left floating.
23 LDO_I power_in Power input pin of the LDO; recommended 1uF MLCC between LDO_I and LDO_G. Input range 2.7V to 5.5V.
24 LDO_O output Output pin of the LDO; LDO output is set through LDO_FB with a resistor divider.
25 Exposed Pad power_in Exposed pad must be soldered to a large PCB copper plane and connected to GND for appropriate dissipation.

Key specifications

Parameter Value
Manufacturer Everanalog IC design
Package QFN-24-EP(4x4)
Category Power Management (PMIC)
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage VINX 2.7 5.5 V 5
Control Circuit Input Voltage VVCC 2.7 5.5 V 5
Buck 1 Shutdown Supply Current ISD1 0.1 1 uA VEN1 = 0V 5
Buck 1 Quiescent Current IQ1 100 150 uA Non-switching, No Load 5
Buck 1 UVLO Threshold VUVLO1 1.7 2 2.2 V VVIN1 Rising 5
Buck 1 Reference Voltage VREF1 0.588 0.6 0.612 V 5
Buck 1 Reference Voltage Range 0.58 0.8 V VID control, 5mV steps 5
Buck 1 Switching Frequency FSW1 1.2 1.5 1.8 MHz ILOAD1 = 300mA 5
Buck 1 PMOS Current Limit ILIM1-P 4.5 5.5 A 5
Buck 1 Enable Pin Input Low Voltage VEN1-L 0.4 V 5
Buck 1 Enable Pin Input High Voltage VEN1-H 2 V 5
Buck 2 Shutdown Supply Current ISD2 0.1 1 uA VEN2 = 0V 5
Buck 2 Quiescent Current IQ2 100 150 uA Non-switching, No Load 5
Buck 2 UVLO Threshold VUVLO2 1.7 2 2.2 V VVIN2 Rising 5
Buck 2 Reference Voltage VREF2 0.588 0.6 0.612 V 6
Buck 2 Reference Voltage Range 0.58 0.8 V VID control, 5mV steps 6
Buck 2 Switching Frequency FSW2 1.2 1.5 1.8 MHz ILOAD1 = 300mA 6
Buck 2 PMOS Current Limit ILIM1-P 2.5 3 A 6
Buck 2 Enable Pin Input Low Voltage VEN2-L 0.4 V 6
Buck 2 Enable Pin Input High Voltage VEN2-H 2 V 6
Buck 3 Shutdown Supply Current ISD3 0.1 1 uA VEN3 = 0V 6
Buck 3 Quiescent Current IQ3 100 150 uA Non-switching, No Load 6
Buck 3 UVLO Threshold VUVLO3 1.7 2 2.2 V VVIN1 Rising 6
Buck 3 Reference Voltage VREF3 0.588 0.6 0.612 V 6
Buck 3 Reference Voltage Range 0.58 0.8 V VID control, 5mV steps 6
Buck 3 Switching Frequency FSW3 1.2 1.5 1.8 MHz ILOAD1 = 300mA 6
Buck 3 PMOS Current Limit ILIM3-P 3 4 A 6
Buck 3 Enable Pin Input Low Voltage VEN3-L 0.4 V 6
Buck 3 Enable Pin Input High Voltage VEN3-H 2 V 7
LDO Standby Current IST 0.1 1 uA LDO_EN short to GND 7
LDO Quiescent Current IQ_LDO 100 150 uA IOUT = 0A 7
LDO Feedback Voltage VFB_LDO 0.588 0.6 0.612 V 7
LDO Reference Voltage Range 0.58 0.8 V VID control, 5mV steps 7
LDO Dropout Voltage VDROP 50 65 mV IOUT = 300mA 7
LDO Enable Pin Input Low Voltage VEN_LDO-L 0.4 V 7
LDO Enable Pin Input High Voltage VEN_LDO-H 1.5 V 7
I2C Input High Voltage VIH 1.5 V 7
I2C Input Low Voltage VIL 0.4 V 7
SDA Output Low Voltage VOL_SDA 0.4 V Open drain, Sink current = 3mA 7
Input Voltage (absolute maximum) VVIN1, VVIN2, VVIN3, VLDO_I, VVCC -0.3 6.5 V 4
LX Pin Voltage (absolute maximum) VLX1, VLX2, VLX3 -0.3 V 4
All Other Pins Voltage (absolute maximum) -0.3 6.5 V 4
Ambient Temperature Operating Range TA -40 85 °C 4
Maximum Junction Temperature TJmax 150 °C 4
Lead Temperature (Soldering) 260 °C Soldering, 10 sec 4
Storage Temperature Range TS -65 150 °C 4
Input Voltage (recommended) VVIN1, VVIN2, VVIN3, VLDO_I, VVCC 2.7 5.5 V 4
Junction Temperature Range TJ -40 125 °C 4
Buck 1 Output Load Current ILOAD1 3 A 5
Buck 2 Output Load Current ILOAD2 1.5 A 6
Buck 3 Output Load Current ILOAD3 2 A 6
Buck 1 PMOS On-Resistance RDS(ON)1-P 100 mΩ ILOAD1 = 300mA 5
Buck 2 PMOS On-Resistance RDS(ON)2-P 130 mΩ ILOAD = 300mA 6
Buck 3 PMOS On-Resistance RDS(ON)3-P 100 mΩ ILOAD1 = 300mA 6
LDO Current Limit ILIM_LDO 1 A 7
Thermal Shutdown Threshold TOTP 160 °C 7
Thermal Shutdown Hysteresis THYST 30 °C 7
QFN 4x4-24 Thermal Resistance (junction-to-case) θJC 7.5 °C/W 4
QFN 4x4-24 Thermal Resistance (junction-to-ambient) θJA 50 °C/W 4
QFN 4x4-24 Power Dissipation (PDmax) PDmax 2.5 W TA=25°C 4

CAD (KiCad official)

  • Symbol: EA3056QDR
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: ea3056qdr-etched.step / ea3056qdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ea3056qdr.step / ea3056qdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Everanalog IC design datasheet (19 pp, sha256 360806e4997db3dc, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF