component
STM32H563VGT6
Public Made by Adomby adom
ST(意法半导体) Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32H563VGT6
ST(意法半导体) · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
STM32H563VGT6 from ST(意法半导体), in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5 V-tolerant I/O (FT_h); after reset the pin is a GPIO with alternate functions such as TRACECLK, LPTIM1_IN2, SAI1_CK1, SPI4_SCK and FMC_A23. |
| 2 | PE3 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include TRACED0, TIM15_BKIN, SAI1_SD_B, USART10_TX and FMC_A19, and it is a tamper input/output (TAMP_IN6/TAMP_OUT3). |
| 3 | PE4 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include TRACED1, SAI1_D2, TIM15_CH1N, SPI4_NSS and FMC_A20, and it is a tamper input/output (TAMP_IN7/TAMP_OUT8). |
| 4 | PE5 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include TRACED2, SAI1_CK2, TIM15_CH1, SPI4_MISO and FMC_A21, and it is a tamper input/output (TAMP_IN8/TAMP_OUT7). |
| 5 | PE6 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include TRACED3, TIM1_BKIN2, SAI1_D1, TIM15_CH2, SPI4_MOSI and FMC_A22, and it is a tamper input/output (TAMP_IN3/TAMP_OUT6). |
| 6 | VBAT | power_in | Backup-domain supply for the RTC, the 32 backup registers and the VBAT mode; VBAT is listed as a main power pin that must always be connected (Table 17 note 1). |
| 7 | PC13 | bidirectional | 5 V-tolerant I/O (FT_t) supplied through the power switch (VSW): output speed must not exceed 2 MHz with a 30 pF maximum load and it must not be used as a current source; it is a tamper input/output (TAMP_IN1/TAMP_OUT2/TAMP_OUT3) and also RTC_OUT1/RTC_TS and WKUP4, and as a tamper it is functional in Standby and VBAT modes. |
| 8 | PC14-OSC32_IN | bidirectional | 5 V-tolerant I/O (FT) supplied through the power switch (VSW) with the same output limits as PC13 (2 MHz, 30 pF, no current source use); it is the OSC32_IN low-speed oscillator input (LSE, 32.768 kHz). |
| 9 | PC15-OSC32_OUT | bidirectional | 5 V-tolerant I/O (FT) supplied through the power switch (VSW) with the same output limits as PC13 (2 MHz, 30 pF, no current source use); it is the OSC32_OUT low-speed oscillator output (LSE, 32.768 kHz). |
| 10 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground (Table 17 note 1). |
| 11 | VDD | power_in | Digital supply pin with a standard operating range of 1.71 V to 3.6 V (1.71 V to 2.7 V when HSLV = 1); all VDD pins must be connected (Table 20, Table 17 note 1). |
| 12 | PH0-OSC_IN | bidirectional | 5 V-tolerant I/O (FT); it is the OSC_IN input of the 4-50 MHz HSE external oscillator, with EVENTOUT as an alternate function. |
| 13 | PH1-OSC_OUT | bidirectional | 5 V-tolerant I/O (FT); it is the OSC_OUT output of the 4-50 MHz HSE external oscillator, with EVENTOUT as an alternate function. |
| 14 | NRST | bidirectional | Bidirectional reset pin (RST structure) with an embedded weak pull-up resistor. |
| 15 | PC0 | bidirectional | 5 V-tolerant I/O (FT_a) with analog switch function supplied by VDDA; it is also ADC12_INP10 and has alternate functions such as TIM16_BKIN, SAI1_MCLK_A, SPI2_RDY and FMC_SDNWE. |
| 16 | PC1 | bidirectional | 5 V-tolerant I/O (FT_ah) with analog switch function supplied by VDDA; additional functions are ADC12_INP11, ADC12_INN10, TAMP_IN3/TAMP_OUT5 and WKUP6, and alternate functions include TRACED0, SAI1_SD_A and ETH_MDC. |
| 17 | PC2 | bidirectional | 5 V-tolerant I/O (FT_a) with analog switch function supplied by VDDA; additional functions are ADC12_INP12 and ADC12_INN11, and alternate functions include PWR_CSLEEP, TIM17_CH1, SPI2_MISO/I2S2_SDI and OCTOSPI1_IO5. |
| 18 | PC3 | bidirectional | 5 V-tolerant I/O (FT_a) with analog switch function supplied by VDDA; additional functions are ADC12_INP13 and ADC12_INN12, and alternate functions include PWR_CSTOP, SAI1_D3, LPTIM3_CH1 and ETH_MII_TX_CLK. |
| 19 | VSSA | power_in | Analog ground pin for the analog domain (ADC, DAC, reference), which must be connected like the other ground pins (Table 17 note 1). |
| 20 | VREF- | power_in | Negative voltage reference pin for the ADC, listed as a supply pin in the pin definition table. |
| 21 | VREF+ | power_in | Positive voltage reference input for ADC and DAC; VREF+ may exceed VDDA by at most 0.4 V (Table 17). |
| 22 | VDDA | power_in | Analog supply for the ADC, DAC and other analog blocks; VDDx - VSS must not exceed 4.0 V (Table 17). |
| 23 | PA0 | bidirectional | 5 V-tolerant I/O (FT_at) with analog switch function supplied by VDDA; it is a tamper input in Standby/VBAT modes, with additional functions ADC12_INP0, ADC12_INN1, TAMP_IN2/TAMP_OUT1 and WKUP1, and alternate functions such as TIM2_CH1, SPI6_NSS and USART2_CTS. |
| 24 | PA1 | bidirectional | 5 V-tolerant I/O (FT_aht) with analog switch function supplied by VDDA; it is a tamper input/output in Standby/VBAT modes, with additional functions ADC12_INP1 and TAMP_IN5/TAMP_OUT4, and alternate functions such as TIM2_CH2, LPTIM1_IN1 and OCTOSPI1_DQS. |
| 25 | PA2 | bidirectional | 5 V-tolerant I/O (FT_hat) with analog switch function supplied by VDDA; it is a tamper input in Standby/VBAT modes, with additional functions ADC12_INP14, TAMP_IN4/TAMP_OUT3 and WKUP2, and alternate functions such as TIM2_CH3, LPTIM1_IN2 and USART2_TX. |
| 26 | PA3 | bidirectional | 5 V-tolerant I/O (FT_ah) with analog switch function supplied by VDDA; additional function ADC12_INP15, and alternate functions include TIM2_CH4, OCTOSPI1_CLK, SPI2_NSS/I2S2_WS and USART2_RX. |
| 27 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground (Table 17 note 1). |
| 28 | VDD | power_in | Digital supply pin with a standard operating range of 1.71 V to 3.6 V (1.71 V to 2.7 V when HSLV = 1); all VDD pins must be connected (Table 20). |
| 29 | PA4 | bidirectional | 3.6 V-tolerant I/O (TT_a) with analog switch function supplied by VDDA; additional functions are ADC12_INP18 and DAC1_OUT1, and alternate functions include TIM5_ETR, SPI1_NSS/I2S1_WS and SPI6_NSS. |
| 30 | PA5 | bidirectional | 3.6 V-tolerant I/O (TT_ah) with analog switch function supplied by VDDA; additional functions are ADC12_INP19, ADC12_INN18 and DAC1_OUT2, and alternate functions include TIM2_CH1, SPI1_SCK/I2S1_CK and ETH_MII_TX_EN. |
| 31 | PA6 | bidirectional | 5 V-tolerant I/O (FT_ah) with analog switch function supplied by VDDA; additional function ADC12_INP3, and alternate functions include TIM1_BKIN, TIM3_CH1, SPI1_MISO/I2S1_SDI and OCTOSPI1_IO3. |
| 32 | PA7 | bidirectional | 5 V-tolerant I/O (FT_ah) with analog switch function supplied by VDDA; additional functions are ADC12_INP7 and ADC12_INN3, and alternate functions include TIM1_CH1N, TIM3_CH2, SPI1_MOSI/I2S1_SDO and FMC_NWE. |
| 33 | PC4 | bidirectional | 5 V-tolerant I/O (FT_a) with analog switch function supplied by VDDA; additional function ADC12_INP4, and alternate functions include TIM2_CH4, SAI1_CK1, LPTIM2_ETR and FMC_SDNE0. |
| 34 | PC5 | bidirectional | 5 V-tolerant I/O (FT_ah) with analog switch function supplied by VDDA; additional functions are ADC12_INP8 and ADC12_INN4, and alternate functions include TIM1_CH4N, SAI1_D3, PSSI_D15 and OCTOSPI1_DQS. |
| 35 | PB0 | bidirectional | 5 V-tolerant I/O (FT_ah) with analog switch function supplied by VDDA; additional functions are ADC12_INP9 and ADC12_INN5, and alternate functions include TIM1_CH2N, TIM3_CH3, OCTOSPI1_IO1 and ETH_MII_RXD2. |
| 36 | PB1 | bidirectional | 5 V-tolerant I/O (FT_ah) with analog switch function supplied by VDDA; additional function ADC12_INP5, and alternate functions include TIM1_CH3N, TIM3_CH4, OCTOSPI1_IO0 and ETH_MII_RXD3. |
| 37 | PB2 | bidirectional | 5 V-tolerant I/O (FT_ah) with analog switch function supplied by VDDA; additional function LSCO, and alternate functions include RTC_OUT2, SAI1_D1, SPI1_RDY, LPTIM1_CH1 and OCTOSPI1_CLK. |
| 38 | PE7 | bidirectional | 5 V-tolerant I/O (FT_ah) with analog switch function supplied by VDDA; alternate functions include TIM1_ETR, UART7_RX, OCTOSPI1_IO4 and FMC_D4/FMC_AD4. |
| 39 | PE8 | bidirectional | 5 V-tolerant I/O (FT_ah) with analog switch function supplied by VDDA; alternate functions include TIM1_CH1N, UART7_TX, OCTOSPI1_IO5 and FMC_D5/FMC_AD5. |
| 40 | PE9 | bidirectional | 5 V-tolerant I/O (FT_ah) with analog switch function supplied by VDDA; alternate functions include TIM1_CH1, UART7_RTS/UART7_DE, OCTOSPI1_IO6 and FMC_D6/FMC_AD6. |
| 41 | PE10 | bidirectional | 5 V-tolerant I/O (FT_ah) with analog switch function supplied by VDDA; alternate functions include TIM1_CH2N, UART7_CTS, OCTOSPI1_IO7 and FMC_D7/FMC_AD7. |
| 42 | PE11 | bidirectional | 5 V-tolerant I/O (FT_ah) with analog switch function supplied by VDDA; alternate functions include TIM1_CH2, SPI1_RDY, SPI4_NSS, OCTOSPI1_NCS and FMC_D8/FMC_AD8. |
| 43 | PE12 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include TIM1_CH3N, SPI4_SCK, SAI2_SCK_B and FMC_D9/FMC_AD9. |
| 44 | PE13 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include TIM1_CH3, SPI4_MISO, SAI2_FS_B and FMC_D10/FMC_AD10. |
| 45 | PE14 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include TIM1_CH4, SPI4_MOSI, SAI2_MCLK_B and FMC_D11/FMC_AD11. |
| 46 | PE15 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include TIM1_BKIN, TIM1_CH4N, USART10_CK and FMC_D12/FMC_AD12. |
| 47 | PB10 | bidirectional | 5 V-tolerant Fm+ capable I/O (FT_f); alternate functions include TIM2_CH3, LPTIM3_CH1, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX and OCTOSPI1_NCS. |
| 48 | VCAP | power_in | Connection for the external capacitor that stabilizes the embedded LDO regulator; two VCAP pins must be connected to external capacitors (Section 5.3.2). |
| 49 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground (Table 17 note 1). |
| 50 | VDD | power_in | Digital supply pin with a standard operating range of 1.71 V to 3.6 V (1.71 V to 2.7 V when HSLV = 1); all VDD pins must be connected (Table 20). |
| 51 | PB12 | bidirectional | 5 V-tolerant Fm+ capable I/O (FT_fh); alternate functions include TIM1_BKIN, OCTOSPI1_NCLK, I2C2_SDA, SPI2_NSS/I2S2_WS, USART3_CK, FDCAN2_RX and UART5_RX. |
| 52 | PB13 | bidirectional | I/O with FT_c structure (5.5 V maximum input, USB Type-C PD function); alternate functions include TIM1_CH1N, LPTIM3_IN1, I2C2_SMBA, SPI2_SCK/I2S2_CK, FDCAN2_TX and UART5_TX, its output timing is given in Table 67, and it has the UCPD1_CC1 additional function. |
| 53 | PB14 | bidirectional | I/O with FT_c structure (5.5 V maximum input, USB Type-C PD function); alternate functions include TIM1_CH2N, TIM12_CH1, USART1_TX, SPI2_MISO/I2S2_SDI and SDMMC2_D0, its output timing is given in Table 67, and it has the UCPD1_CC2 additional function. |
| 54 | PB15 | bidirectional | 5 V-tolerant Fm+ I/O (FT_h); additional function PVD_IN, and alternate functions include RTC_REFIN, TIM1_CH3N, USART1_RX, SPI2_MOSI/I2S2_SDO and OCTOSPI1_CLK. |
| 55 | PD8 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include USART3_TX and FMC_D13/FMC_AD13. |
| 56 | PD9 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include USART3_RX, FDCAN2_RX and FMC_D14/FMC_AD14. |
| 57 | PD10 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include LPTIM2_CH2, USART3_CK and FMC_D15/FMC_AD15. |
| 58 | PD11 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include SAI1_CK1, LPTIM2_IN2, USART3_CTS/USART3_NSS, OCTOSPI1_IO0 and FMC_A16/FMC_CLE. |
| 59 | PD12 | bidirectional | 5 V-tolerant Fm+ I/O (FT_fh); alternate functions include LPTIM1_IN1, TIM4_CH1, I2C4_SCL, I3C1_SCL, USART3_RTS/USART3_DE and FMC_A17/FMC_ALE, and it has the DCMI_D12/PSSI_D12 additional function. |
| 60 | PD13 | bidirectional | 5 V-tolerant Fm+ I/O (FT_fh); alternate functions include LPTIM1_CH1, TIM4_CH2, I2C4_SDA, I3C1_SDA, OCTOSPI1_IO3 and FMC_A18. |
| 61 | PD14 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include TIM4_CH3, UART8_CTS, UART9_RX and FMC_D0/FMC_AD0. |
| 62 | PD15 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include TIM4_CH4, UART8_RTS/UART8_DE, UART9_TX and FMC_D1/FMC_AD1. |
| 63 | PC6 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include TIM3_CH1, TIM8_CH1, I2S2_MCK, SAI1_SCK_A, USART6_TX and FMC_NWAIT. |
| 64 | PC7 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include TRGIO, TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX and FMC_NE1. |
| 65 | PC8 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include TRACED1, TIM3_CH3, TIM8_CH3, USART6_CK, UART5_RTS/UART5_DE and FMC_NE2/FMC_NCE. |
| 66 | PC9 | bidirectional | 5 V-tolerant Fm+ I/O (FT_fh) with USB Type-C PD dead-battery function (UCPD1_DB2); alternate functions include MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, AUDIOCLK and OCTOSPI1_IO0. |
| 67 | PA8 | bidirectional | 5 V-tolerant Fm+ I/O (FT_fh); alternate functions include MCO1, TIM1_CH1, I2C3_SCL, SPI1_RDY, USART1_CK and USB_SOF. |
| 68 | PA9 | bidirectional | I/O with FT_d structure (5 V-tolerant, USB Type-C PD dead-battery function, UCPD1_DB1); alternate functions include TIM1_CH2, LPUART1_TX, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX and ETH_MII_TX_ER. |
| 69 | PA10 | bidirectional | 5 V-tolerant Fm+ I/O (FT_h); alternate functions include TIM1_CH3, LPUART1_RX, LPTIM2_IN2, UCPD1_FRSTX, USART1_RX and FDCAN2_TX. |
| 70 | PA11 | bidirectional | I/O with FT_u structure (USB function supplied by VDDUSB); alternate functions include TIM1_CH4, LPUART1_CTS, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS/USART1_NSS and FDCAN1_RX, and it carries the USB_DM function. |
| 71 | PA12 | bidirectional | I/O with FT_u structure (USB function supplied by VDDUSB); alternate functions include TIM1_ETR, LPUART1_RTS/LPUART1_DE, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS/USART1_DE and FDCAN1_TX, and it carries the USB_DP function. |
| 72 | PA13 | bidirectional | 5 V-tolerant I/O (FT); after reset this pin is the JTMS/SWDIO debug function, and the internal pull-up on PA13 is activated. |
| 73 | VDDUSB | power_in | Supply for the USB full-speed I/Os (the _u structure pins PA11 and PA12) (Table 13, Figure 20). |
| 74 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground (Table 17 note 1). |
| 75 | VDD | power_in | Digital supply pin with a standard operating range of 1.71 V to 3.6 V (1.71 V to 2.7 V when HSLV = 1); all VDD pins must be connected (Table 20). |
| 76 | PA14 | bidirectional | 5 V-tolerant I/O (FT); after reset this pin is the JTCK/SWCLK debug function, and the internal pull-down on PA14 is activated. |
| 77 | PA15 | bidirectional | 5 V-tolerant I/O (FT); after reset this pin is the JTDI debug function, and the internal pull-up on PA15 is activated; alternate functions include TIM2_CH1, SPI1_NSS/I2S1_WS, UART4_RTS/UART4_DE and UART7_TX. |
| 78 | PC10 | bidirectional | 5 V-tolerant Fm+ I/O (FT_h); alternate functions include LPTIM3_ETR, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, OCTOSPI1_IO1 and SDMMC1_D2. |
| 79 | PC11 | bidirectional | 5 V-tolerant Fm+ I/O (FT_h); alternate functions include LPTIM3_IN1, SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, OCTOSPI1_NCS and SDMMC1_D3. |
| 80 | PC12 | bidirectional | 5 V-tolerant Fm+ I/O (FT_h); alternate functions include TRACED3, TIM15_CH1, SPI6_SCK, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX and SDMMC1_CK. |
| 81 | PD0 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include TIM8_CH4N, UART4_RX, FDCAN1_RX, UART9_CTS and FMC_D2/FMC_AD2. |
| 82 | PD1 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include UART4_TX, FDCAN1_TX and FMC_D3/FMC_AD3. |
| 83 | PD2 | bidirectional | 5 V-tolerant I/O (FT_h); additional function WKUP7; alternate functions include TRACED2, TIM3_ETR, TIM15_BKIN, UART5_RX, SDMMC1_CMD and LPTIM4_ETR. |
| 84 | PD3 | bidirectional | 5 V-tolerant I/O (FT_h); additional function WKUP8; alternate functions include SPI2_SCK/I2S2_CK, USART2_CTS/USART2_NSS, FMC_CLK and DCMI_D5/PSSI_D5. |
| 85 | PD4 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include USART2_RTS/USART2_DE, OCTOSPI1_IO4 and FMC_NOE. |
| 86 | PD5 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include TIM1_CH4N, SPI2_RDY, USART2_TX, FDCAN1_TX, OCTOSPI1_IO5 and FMC_NWE. |
| 87 | PD6 | bidirectional | 5 V-tolerant I/O (FT_sh) supplied only by VDDIO2 (Table 13); alternate functions include SAI1_D1, SPI3_MOSI/I2S3_SDO, USART2_RX, OCTOSPI1_IO6 and FMC_NWAIT. |
| 88 | PD7 | bidirectional | 5 V-tolerant I/O (FT_sh) supplied only by VDDIO2 (Table 13); alternate functions include SPI1_MOSI/I2S1_SDO, USART2_CK, OCTOSPI1_IO7, SDMMC2_CMD and FMC_NE1/FMC_NCE. |
| 89 | PB3 | bidirectional | 5 V-tolerant Fm+ I/O (FT_fh); after reset this pin is the JTDO/TRACESWO debug function; alternate functions include TIM2_CH2, I2C2_SDA, SPI1_SCK/I2S1_CK, SPI6_SCK and LPTIM6_ETR. |
| 90 | PB4 | bidirectional | 5 V-tolerant I/O (FT_h); after reset this pin is the NJTRST debug function, and the internal pull-up on PB4 is activated; alternate functions include TIM16_BKIN, TIM3_CH1, OCTOSPI1_CLK, LPTIM1_CH2 and SPI1_MISO/I2S1_SDI. |
| 91 | PB5 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include TIM17_BKIN, TIM3_CH2, OCTOSPI1_NCLK, I2C1_SMBA, SPI1_MOSI/I2S1_SDO and FDCAN2_RX. |
| 92 | PB6 | bidirectional | 5 V-tolerant Fm+ I/O (FT_f); alternate functions include TIM16_CH1N, TIM4_CH1, I3C1_SCL, I2C1_SCL, USART1_TX, LPUART1_TX and FDCAN2_TX. |
| 93 | PB7 | bidirectional | 5 V-tolerant Fm+ I/O (FT_fa) with analog switch function supplied by VDDA; additional function WKUP5; alternate functions include TIM17_CH1N, TIM4_CH2, I3C1_SDA, I2C1_SDA, USART1_RX and LPUART1_RX. |
| 94 | BOOT0 | input | Boot pin (input-only, B structure) used for boot-mode selection; its input voltage is limited to VSS - 0.3 V up to min(min(VDD, VDDA, VDDUSB, VDDIO2) + 4.0 V, 6.0 V) (Table 17). |
| 95 | PB8 | bidirectional | 5 V-tolerant Fm+ I/O (FT_fhs) supplied only by VDDIO2 (Table 13); alternate functions include TIM16_CH1, TIM4_CH3, I3C1_SCL, I2C1_SCL, SPI4_RDY, UART4_RX and FDCAN1_RX. |
| 96 | PB9 | bidirectional | 5 V-tolerant Fm+ I/O (FT_fhs) supplied only by VDDIO2 (Table 13); alternate functions include TIM17_CH1, TIM4_CH4, I3C1_SDA, I2C1_SDA, SPI2_NSS/I2S2_WS, UART4_TX and FDCAN1_TX. |
| 97 | PE0 | bidirectional | 5 V-tolerant I/O (FT_h); alternate functions include LPTIM1_ETR, TIM4_ETR, LPTIM2_CH2, SPI3_RDY, UART8_RX, FDCAN1_RX and FMC_NBL0. |
| 98 | VCAP | power_in | Connection for the external capacitor that stabilizes the embedded LDO regulator; the second VCAP pin must also be connected to an external capacitor (Section 5.3.2). |
| 99 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground (Table 17 note 1). |
| 100 | VDD | power_in | Digital supply pin with a standard operating range of 1.71 V to 3.6 V (1.71 V to 2.7 V when HSLV = 1); all VDD pins must be connected (Table 20). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ST(意法半导体) |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDDx to VSS (external main supply, including VDDA, VDDUSB, VDDIO2, VBAT, VREF+) | VDDx - VSS | -0.3 | 4 | V | External main supply pins | 124 | |
| Input voltage on TT_xx pins | VIN | -0.3 | 4 | V | TT_xx pins; min printed as VSS - 0.3 | 124 | |
| Input voltage on any other pins | VIN | -0.3 | 4 | V | Any other pins not listed separately; min printed as VSS - 0.3 | 124 | |
| Input voltage on FT_c pins | VIN | -0.3 | 5.5 | V | FT_c pins; min printed as VSS - 0.3 | 124 | |
| Allowed voltage difference for VREF+ > VDDA | VREF+-VDDA | 0.4 | V | VREF+ > VDDA | 124 | ||
| Variations between different VDDX power pins of the same domain | /ΔVDDx/ | 50 | mV | Same domain | 124 | ||
| Variations between all the different ground pins | /VSSx-VSS/ | 50 | mV | All ground pins | 124 | ||
| Total current into sum of all VDD power lines (source) | ∑IVDD | 350 | mA | 125 | |||
| Total current out of sum of all VSS ground lines (sink) | ∑IVSS | 350 | mA | 125 | |||
| Maximum current into each VDD power pin (source) | IVDD | 100 | mA | Each VDD pin | 125 | ||
| Maximum current out of each VSS ground pin (sink) | IVSS | 100 | mA | Each VSS pin | 125 | ||
| Output current sunk/sourced by any I/O and control pin | IIO(PIN) | 20 | mA | 125 | |||
| Total output current sunk by sum of all I/Os and control pins | ∑IIO(PIN) | 140 | mA | 125 | |||
| Total output current sourced by sum of all I/Os and control pins | ∑IIO(PIN) | 140 | mA | 125 | |||
| Injected current on FT_xxx, TT_xx, NRST pins | IINJ(PIN) | -5 | 0 | mA | FT_xxx, TT_xx, NRST pins | 125 | |
| Total injected current (sum of all I/Os and control pins) | ∑/IINJ(PIN)/ | -25 | 25 | mA | 125 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 125 | ||
| Maximum junction temperature | TJ | 130 | °C | Limited to 105 °C in VOS0 voltage range | 125 | ||
| Standard operating voltage | VDD | 1.71 | 3.6 | V | HSLV = 0 | 125 | |
| Standard operating voltage | VDD | 1.71 | 2.7 | V | HSLV = 1 | 125 | |
| I/O supply voltage (PB8, PB9, PD6, PD7, PG[9:14]) | VDDIO2 | 1.08 | 3.6 | V | At least one I/O in PB8, PB9, PD6, PD7, PG[9:14] used, HSLV = 0 | 126 | |
| I/O supply voltage (PB8, PB9, PD6, PD7, PG[9:14]) | VDDIO2 | 1.08 | 2.7 | V | At least one I/O in PB8, PB9, PD6, PD7, PG[9:14] used, HSLV = 1 | 126 | |
| USB supply voltage | VDDUSB | 3 | 3.6 | V | USB is used | 126 | |
| Analog supply voltage | VDDA | 1.62 | 3.6 | V | ADC is used | 126 | |
| Analog supply voltage | VDDA | 1.8 | 3.6 | V | DAC is used | 126 | |
| Analog supply voltage | VDDA | 2.1 | 3.6 | V | VREFBUF is used | 126 | |
| Backup domain supply voltage | VBAT | 1.2 | 3.6 | V | 126 | ||
| I/O input voltage on FT_c I/O | VIN | -0.3 | 5 | V | FT_c I/O | 126 | |
| Internal regulator ON, VCORE | VCORE | 1.3 | 1.35 | 1.4 | V | VOS0, max frequency for AHB and APB 250 MHz | 127 |
| Internal regulator ON, VCORE | VCORE | 1.15 | 1.2 | 1.26 | V | VOS1, max frequency for AHB and APB 200 MHz | 127 |
| Internal regulator ON, VCORE | VCORE | 1.05 | 1.1 | 1.15 | V | VOS2, max frequency for AHB and APB 150 MHz | 127 |
| Internal regulator ON, VCORE | VCORE | 0.95 | 1 | 1.05 | V | VOS3, max frequency for AHB and APB 100 MHz | 127 |
| Regulator OFF, external VCORE supplied on VCAP pins | VCORE | 1.32 | 1.35 | 1.4 | V | VOS0 | 127 |
| Regulator OFF, external VCORE supplied on VCAP pins | VCORE | 1.17 | 1.2 | 1.26 | V | VOS1 | 127 |
| Regulator OFF, external VCORE supplied on VCAP pins | VCORE | 1.07 | 1.1 | 1.15 | V | VOS2 | 127 |
| Regulator OFF, external VCORE supplied on VCAP pins | VCORE | 0.97 | 1 | 1.05 | V | VOS3 | 127 |
| AHB clock frequency fHCLK | fHCLK | 250 | MHz | VOS0 | 127 | ||
| AHB clock frequency fHCLK | fHCLK | 200 | MHz | VOS1 | 127 | ||
| AHB clock frequency fHCLK | fHCLK | 150 | MHz | VOS2 | 127 | ||
| AHB clock frequency fHCLK | fHCLK | 100 | MHz | VOS3 | 127 | ||
| Ambient temperature for the suffix 6 version | TA | -40 | 85 | °C | Maximum power dissipation | 128 | |
| Ambient temperature for the suffix 6 version | TA | -40 | 125 | °C | In LDO bypass mode | 128 | |
| Junction temperature range | TJ | -40 | 105 | °C | VOS0 | 128 | |
| Junction temperature range | TJ | -40 | 130 | °C | VOS1, VOS2, and VOS3 | 128 | |
| Internal reference voltage | VREFINT | 1.18 | 1.216 | 1.255 | V | -40 °C < TJ < +130 °C | 135 |
| Internal reference voltage spread over the temperature range | ∆VREFINT | 5 | 15 | mV | -40 °C < TJ < +130 °C | 135 | |
| Average temperature coefficient | TCoeff | 20 | 70 | ppm/°C | 135 | ||
| Average voltage coefficient | VDDcoeff | 10 | 1370 | ppm/V | 3.0 V < VDD < 3.6 V | 135 | |
| Power-on/down reset threshold (BORH_EN = 0), rising edge | VPOR/PDR | 1.62 | 1.67 | 1.71 | V | Rising edge, BORH_EN = 0 | 133 |
| Power-on/down reset threshold (BORH_EN = 0), falling edge | VPOR/PDR | 1.58 | 1.62 | 1.68 | V | Falling edge, BORH_EN = 0 | 133 |
| Brownout reset threshold 1 (BORH_EN = 1), rising edge | VBOR1 | 2.04 | 2.1 | 2.15 | V | Rising edge, BORH_EN = 1 | 133 |
| Brownout reset threshold 1 (BORH_EN = 1), falling edge | VBOR1 | 1.95 | 2 | 2.06 | V | Falling edge, BORH_EN = 1 | 133 |
| Supply current in Run mode, fHCLK 250 MHz | IDD(Run) | 32.1 | 87 | mA | VOS0, all peripherals disabled, code from flash, 2-way I-cache, TJ = 105 °C, LDO; typ LDO | 136 | |
| Supply current in Run mode, fHCLK 200 MHz | IDD(Run) | 22.1 | 62 | mA | VOS1, all peripherals disabled, code from flash, 2-way I-cache, TJ = 105 °C, LDO; typ LDO | 136 | |
| Supply current in Run mode, fHCLK 150 MHz | IDD(Run) | 15.4 | 47 | mA | VOS2, all peripherals disabled, code from flash, 2-way I-cache, TJ = 105 °C, LDO; typ LDO | 136 | |
| Supply current in Run mode, fHCLK 100 MHz | IDD(Run) | 9.8 | 34 | mA | VOS3, all peripherals disabled, code from flash, 2-way I-cache, TJ = 105 °C, LDO; typ LDO | 136 | |
| Supply current in Sleep mode, fHCLK 250 MHz | IDD(sleep) | 7.3 | 61 | mA | VOS0, all peripherals disabled, TJ = 105 °C, LDO; typ LDO | 140 |
CAD (KiCad official)
- Symbol:
STM32H563VGT6 - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
stm32h563vgt6-etched.step/stm32h563vgt6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32h563vgt6.step/stm32h563vgt6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ST(意法半导体) datasheet (270 pp, sha256
fc24f0be69fd186b, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).