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CBM8551AS8

Corebai Microelectronics · Precision OpAmps · SOIC-8

CBM8551AS8 from Corebai Microelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection. May be left floating or tied to any potential within the absolute maximum ratings; typically left unconnected.
2 IN- input Inverting analog input of the op-amp. Rail-to-rail common-mode range extending 100mV beyond the supply rails (VSS-0.1V to VDD+0.1V). Very low input bias current (~20pA typical).
3 IN+ input Non-inverting analog input of the op-amp. Rail-to-rail common-mode range extending 100mV beyond the supply rails (VSS-0.1V to VDD+0.1V). Very low input bias current (~20pA typical).
4 VSS power_in Negative supply rail / ground. Total supply (VDD-VSS) range 1.8V to 5.5V (absolute max 7.5V). Bypass to VDD with a 0.1µF ceramic capacitor placed close to the device; for dual-supply operation bypass both VDD and VSS to ground separately.
5 NC unconnected No internal connection. May be left floating or tied to any potential within the absolute maximum ratings; typically left unconnected.
6 OUT output Op-amp output. Rail-to-rail output swing; typically within 5mV of the rails into >100kΩ loads and within 60mV into 10kΩ. Short-circuit current ~60mA, output current up to ~65mA.
7 VDD power_in Positive supply rail. Single-supply range 1.8V to 5.5V referenced to VSS (absolute max VDD-VSS = 7.5V). Place a 0.1µF ceramic bypass capacitor close to this pin.
8 NC unconnected No internal connection. May be left floating or tied to any potential within the absolute maximum ratings; typically left unconnected.

Key specifications

Parameter Value
Manufacturer Corebai Microelectronics
Package SOIC-8
Category Op-amp/Cmp
Pins 8

Ordering variants

  • CBM8551AS8
  • CBM8551AS8AST5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Offset Voltage VOS 1 30 µV VS=+5V, VCM=+2.5V, VO=+2.5V, TA=+25℃ 4
Power Supply Voltage (VDD to VSS) -0.5 7.5 V VDD to VSS 3
PDB Input Voltage 7 V 3
Operating Temperature Range -45 125 ℃ 3
Junction Temperature 160 ℃ 3
Storage Temperature Range -55 150 ℃ 3
Lead Temperature (soldering) 260 ℃ 10 sec 3
ESD Susceptibility HBM 6 KV HBM 3
ESD Susceptibility MM 400 V MM 3
Package Thermal Resistance SOP-8 θJA 125 ℃/W TA=+25℃ 3
Input Bias Current IB 20 pA 4
Input Offset Current IOS 10 pA 4
Common-Mode Rejection Ratio CMRR 110 dB VCM = 0V to 5V 4
Large Signal Voltage Gain AVO 145 dB RL = 10kΩ, VO = 0.3V to 4.7V 4
Input Offset Voltage Drift ∆VOS/∆T 30 nV/℃ 4
Output Voltage High VOH 4.998 V RL = 100kΩ to - VS 4
Output Voltage High VOH 4.994 V RL = 10kΩ to - VS 4
Output Voltage Low VOL 2 mV RL = 100kΩ to + VS 4
Output Voltage Low VOL 5 mV RL = 10kΩ to + VS 4
Short Circuit Limit ISC 60 mA RL =10Ω to - VS 4
Output Current IO 65 mA 4
Power Supply Rejection Ratio PSRR 115 dB VS = 2.5V to 5.5V 4
Quiescent Current IQ 180 µA VO = 0V, RL = 0Ω 4
Gain-Bandwidth Product GBP 1.8 MHz G = +100 4
Slew Rate SR 0.95 V/μs RL = 10kΩ 4
Overload Recovery Time 0.1 ms 4
Voltage Noise (en p-p) en p-p 0.3 µVp-p 0Hz to 10Hz 4
Voltage Noise Density en 38 nV/√Hz f = 1kHz 4

CAD (KiCad official)

  • Symbol: CBM8551AS8
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: cbm8551as8-etched.step / cbm8551as8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cbm8551as8.step / cbm8551as8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Corebai Microelectronics datasheet (None pp, sha256 f2188dc09cf52931, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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