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PIC16LF18425-I
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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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Datasheet
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Contents
README
markdownPIC16LF18425-I
Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · SOIC-14
PIC16LF18425-I from Microchip Tech, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply voltage pin that must always be connected and decoupled with a 0.1 µF capacitor placed close to the pin. |
| 2 | RA5 | bidirectional | PORTA bit 5 general-purpose I/O with analog input ANA5, interrupt-on-change IOCA5 and weak pull-up; also CLKIN/OSC1/SOSCI, and default PPS input for T1CKI, T2IN, SMT1SIG and CLCIN3. |
| 3 | RA4 | bidirectional | PORTA bit 4 general-purpose I/O with analog input ANA4, interrupt-on-change IOCA4 and weak pull-up; also CLKOUT/OSC2/SOSCO, and default PPS input for T1G and SMT1WIN. |
| 4 | RA3/MCLR/VPP | input | Input-only pin that works as PORTA bit 3 digital input or as Master Clear reset (MCLR) when enabled, and also serves as the programming voltage input (VPP) during high-voltage programming. |
| 5 | RC5 | bidirectional | PORTC bit 5 general-purpose I/O with analog input ANC5, interrupt-on-change IOCC5 and weak pull-up; default PPS input for CCP1IN, T3CKI, MDCARH, SDI2/SDA2 and RX1/DT1. |
| 6 | RC4 | bidirectional | PORTC bit 4 general-purpose I/O with analog input ANC4, interrupt-on-change IOCC4 and weak pull-up; default PPS input for T3G, SCK2/SCL2, CK1 and CLCIN1. |
| 7 | RC3 | bidirectional | PORTC bit 3 general-purpose I/O with analog input ANC3 and comparator inputs C1IN3-/C2IN3-, interrupt-on-change IOCC3 and weak pull-up; default PPS input for T5G, CCP2IN, SS1 and CLCIN0. |
| 8 | RC2 | bidirectional | PORTC bit 2 general-purpose I/O with analog input ANC2 and comparator inputs C1IN2-/C2IN2-, ADACT trigger and MDCARL, interrupt-on-change IOCC2 and weak pull-up. |
| 9 | RC1 | bidirectional | PORTC bit 1 general-purpose I/O with analog input ANC1 and comparator inputs C1IN1-/C2IN1-, interrupt-on-change IOCC1 and weak pull-up; default PPS input for T4IN, CCP4IN, SDI1/SDA1 and CLCIN2. |
| 10 | RC0 | bidirectional | PORTC bit 0 general-purpose I/O with analog input ANC0 and comparator input C2IN0+, interrupt-on-change IOCC0 and weak pull-up; default PPS input for T5CKI and SCK1/SCL1. |
| 11 | RA2 | bidirectional | PORTA bit 2 general-purpose I/O with analog input ANA2, ADCVREF-, DAC1VREF-, ZCD1, INT and interrupt-on-change IOCA2; default PPS input for T0CKI, CCP3IN, CWG1IN and CWG2IN. |
| 12 | RA1/ICSPCLK | bidirectional | PORTA bit 1 general-purpose I/O with analog input ANA1, ADCVREF+, C1IN0-/C2IN0-, DAC1VREF+ and IOCA1; also ICSPCLK/ICDCLK in-circuit serial programming clock input; default PPS input for MDSRC. |
| 13 | RA0/ICSPDAT | bidirectional | PORTA bit 0 general-purpose I/O with analog input ANA0, C1IN0+, DAC1OUT1 and IOCA0; also ICSPDAT/ICDDAT bidirectional in-circuit programming data pin; default PPS input for SS2. |
| 14 | VSS | power_in | Ground reference pin that must always be connected. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-14 |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating supply voltage (FOSC ≤ 16 MHz) | VDD | 1.8 | 3.6 | V | FOSC ≤ 16 MHz | 631 | |
| Operating supply voltage (FOSC > 16 MHz) | VDD | 2.5 | 3.6 | V | FOSC > 16 MHz | 631 | |
| RAM data retention voltage | VDR | 1.5 | V | Device in Sleep mode | 631 | ||
| Power-on Reset release voltage | VPOR | 1.6 | V | BOR or LPBOR disabled | 632 | ||
| Power-on Reset rearm voltage | VPORR | 0.8 | V | BOR or LPBOR disabled | 632 | ||
| VDD rise rate for POR | SVDD | 0.05 | V/ms | BOR or LPBOR disabled | 632 | ||
| Supply current XT 4 MHz | IDDXT4 | 465 | 670 | μA | XT = 4 MHz, VDD 3.0V | 633 | |
| Supply current HFINTOSC 16 MHz | IDDHFO16 | 2.1 | 2.6 | mA | HFINTOSC = 16 MHz, VDD 3.0V | 633 | |
| Supply current HFINTOSC 32 MHz | IDDHFOPLL | 3.9 | 4.8 | mA | HFINTOSC = 32 MHz, VDD 3.0V | 634 | |
| Supply current HS+PLL 32 MHz | IDDHSPLL32 | 3.6 | 4.4 | mA | HS+PLL = 32 MHz, VDD 3.0V | 634 | |
| Supply current IDLE mode | IDDIDLE | 1.5 | 1.9 | mA | IDLE mode, HFINTOSC = 16 MHz, VDD 3.0V | 634 | |
| Power-down current base (85°C max) | IPD | 0.08 | 2 | μA | IPD Base, VDD 3.0V, max at +85°C | 635 | |
| Power-down current base (125°C max) | IPD | 0.08 | 7 | μA | IPD Base, VDD 3.0V, max at +125°C | 635 | |
| Power-down current LFINTOSC/WDT (85°C) | IPD_WDT | 0.8 | 2.8 | μA | VDD 3.0V, max at +85°C | 635 | |
| Power-down current LFINTOSC/WDT (125°C) | IPD_WDT | 0.8 | 8 | μA | VDD 3.0V, max at +125°C | 635 | |
| Power-down current SOSC (85°C) | IPD_SOSC | 1 | 3.8 | μA | VDD 3.0V, max at +85°C | 635 | |
| Power-down current SOSC (125°C) | IPD_SOSC | 1 | 9 | μA | VDD 3.0V, max at +125°C | 635 | |
| Power-down current FVR (85°C) | IPD_FVR | 46 | 76 | μA | VDD 3.0V, max at +85°C | 635 | |
| Power-down current BOR (85°C) | IPD_BOR | 10 | 15 | μA | VDD 3.0V, max at +85°C | 635 | |
| Power-down current LPBOR (85°C) | IPD_LPBOR | 0.13 | 2.2 | μA | VDD 3.0V, max at +85°C | 635 | |
| Power-down current ADC non-converting (85°C) | IPD_ADCA | 0.08 | 2 | μA | VDD 3.0V, ADC not converting, max at +85°C | 635 | |
| Power-down current comparator (85°C) | IPD_CMP | 30 | 57 | μA | VDD 3.0V, max at +85°C | 635 | |
| Input low voltage, Schmitt Trigger | VIL | 0.2 | V | 2.0V≤VDD≤5.5V; max is 0.2 VDD | 637 | ||
| Input high voltage, Schmitt Trigger | VIH | 0.8 | V | 2.0V≤VDD≤5.5V; min is 0.8 VDD | 637 | ||
| Input leakage current I/O (85°C) | IIL | -125 | 5 | 125 | nA | VSS≤VPIN≤VDD, Pin at high-impedance, 85°C | 637 |
| Input leakage current I/O (125°C) | IIL | -1000 | 5 | 1000 | nA | VSS≤VPIN≤VDD, Pin at high-impedance, 125°C | 637 |
| Weak pull-up current | IPUR | 25 | 120 | 200 | μA | VDD=3.0V, VPIN=VSS | 637 |
| Output low voltage | VOL | 0.6 | V | IOL = 10 mA, VDD = 3.0V | 637 | ||
| I/O pin capacitance | CIO | 5 | 50 | pF | 637 | ||
| Thermal resistance junction to ambient, 14-pin SOIC | θJA | 95.3 | °C/W | 14-pin SOIC package | 639 | ||
| Thermal resistance junction to case, 14-pin SOIC | θJC | 31 | °C/W | 14-pin SOIC package | 640 | ||
| Maximum junction temperature | TJMAX | 150 | °C | 640 | |||
| Brown-out Reset voltage BORV=0 | VBOR | 2.55 | 2.7 | 2.85 | V | BORV=0 | 646 |
| Brown-out Reset voltage BORV=1 (LF) | VBOR | 1.8 | 1.9 | 2.05 | V | BORV=1 (LF devices only) | 646 |
| Low-Power BOR voltage | VLPBOR | 1.8 | 1.9 | 2.2 | V | LF devices only | 646 |
| ADC integral error | EIL | 1 | 2 | LSb | ADCREF+=3.0V, ADCREF-= 0V | 647 | |
| Comparator hysteresis | VHYST | 15 | 25 | 35 | mV | 649 | |
| Ambient temperature under bias | -40 | 125 | °C | 629 | |||
| Storage temperature | -65 | 150 | °C | 629 | |||
| Voltage on VDD pin | VDD | -0.3 | 4 | V | PIC16LF18425/45, with respect to VSS | 629 | |
| Voltage on MCLR pin | -0.3 | 9 | V | with respect to VSS | 629 | ||
| Total power dissipation | 800 | mW | 629 | ||||
| Clamp current | IK | -20 | 20 | mA | VPIN < 0 or VPIN > VDD | 629 | |
| Operating ambient temperature, industrial | TA | -40 | 85 | °C | Industrial | 630 | |
| Operating ambient temperature, extended | TA | -40 | 125 | °C | Extended | 630 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PPS | body RxyPPS | 267 |
CAD (KiCad official)
- Symbol:
PIC16LF18425-I - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
pic16lf18425-i-etched.step/pic16lf18425-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic16lf18425-i.step/pic16lf18425-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (708 pp, sha256
13718a8e0897d6f9, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).