component
AMC3336DWER
Public Made by Adomby adom
TEXAS INSTRUMENTS Global Sourcing Parts, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAMC3336DWER
TEXAS INSTRUMENTS · Global Sourcing Parts · SOIC-16-300mil
AMC3336DWER from TEXAS INSTRUMENTS, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DCDC_OUT | power_out | High-side output of the DC/DC converter; connect this pin to the HLDO_IN pin (pin 3). |
| 2 | DCDC_HGND | power_in | High-side ground reference for the DC/DC converter; connect this pin to the HGND pin (pin 8). |
| 3 | HLDO_IN | power_in | Input of the high-side LDO; connect this pin to the DCDC_OUT pin (pin 1). |
| 4 | NC | unconnected | No internal connection; connect to the high-side ground or leave floating. |
| 5 | HLDO_OUT | power_out | Output of the high-side LDO, which outputs a constant voltage and can provide limited current to external circuitry. |
| 6 | INP | input | Noninverting analog input; either INP or INN must have a DC current path to HGND to define the common-mode input voltage. |
| 7 | INN | input | Inverting analog input; either INP or INN must have a DC current path to HGND to define the common-mode input voltage. |
| 8 | HGND | power_in | High-side analog signal ground; connect this pin to the DCDC_HGND pin (pin 2). |
| 9 | GND | power_in | Low-side analog signal ground; connect this pin to the DCDC_GND pin (pin 15). |
| 10 | DOUT | output | Modulator bitstream data output; the DOUT pin is held permanently low when the high-side supply is lost or in undervoltage. |
| 11 | CLKIN | input | Modulator clock input with internal pull-down resistor (typical value 1.5 MΩ); input clock frequency 9 MHz to 21 MHz with 40% to 60% duty cycle. |
| 12 | VDD | power_in | Low-side power supply, 3 V to 5.5 V per recommended operating conditions; see the Power Supply Recommendations section for decoupling. |
| 13 | LDO_OUT | power_out | Output of the low-side LDO; connect to the DCDC_IN pin (pin 16) and do not load it with external circuitry. |
| 14 | DIAG | output | Active-low, open-drain status indicator output; connect to a pullup supply (for example VDD) through a resistor, or leave floating if not used. |
| 15 | DCDC_GND | power_in | Low-side ground reference for the DC/DC converter; connect this pin to the GND pin (pin 9). |
| 16 | DCDC_IN | power_in | Low-side input of the DC/DC converter; connect this pin to the LDO_OUT pin (pin 13). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TEXAS INSTRUMENTS |
| Package | SOIC-16-300mil |
| Category | Global Sourcing Parts |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power-supply voltage VDD to GND | -0.3 | 6.5 | V | 4 | |||
| Digital output voltage DIAG | 6.5 | V | 4 | ||||
| Input current, continuous, any pin except power-supply pins | -10 | 10 | mA | 4 | |||
| Junction temperature TJ | TJ | 150 | °C | 4 | |||
| Storage temperature Tstg | Tstg | -65 | 150 | °C | 4 | ||
| Power-supply voltage VDD | VDD | 3 | 3.3 | 5.5 | V | VDD to GND | 4 |
| Differential input voltage before clipping | VClipping | -1.25 | 1.25 | V | VIN = VINP, VINN | 4 | |
| Specified linear differential full-scale voltage | VFSR | -1 | 1 | V | VIN = VINP, VINN | 4 | |
| Absolute common-mode input voltage | -2 | V | (VINP + VINN) / 2 to HGND; max is VHLDO_OUT (not numeric) | 4 | |||
| Operating common-mode input voltage | VCM | -0.8 | 0.6 | V | (VINP + VINN) / 2 to HGND | 4 | |
| Digital input / output voltage | VIO | 0 | V | max is VDD (not numeric) | 4 | ||
| Input clock frequency | fCLKIN | 9 | 20 | 21 | MHz | 4 | |
| Input clock duty cycle | 40 | 50 | 60 | % | 9 MHz ≤ fCLKIN ≤ 21 MHz | 4 | |
| Specified ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Maximum power dissipation | PD | 231 | mW | VDD = 5.5 V | 5 | ||
| Maximum power dissipation | PD | 151 | mW | VDD = 3.6 V | 5 | ||
| Single-ended input resistance | RIN | 0.06 | 1 | GΩ | INN = HGND | 8 | |
| Differential input resistance | RIND | 0.06 | 1 | GΩ | 8 | ||
| Input bias current | IIB | -10 | 10 | nA | INP = INN = HGND; IIB = (IIBP + IIBN) / 2 | 8 | |
| Input offset current | IIO | -5 | 0.5 | 5 | nA | IIO = IIBP, IIBN | 8 |
| Offset error | EO | -0.3 | 0.04 | 0.3 | mV | INP = INN = HGND, TA = 25°C | 8 |
| Offset error thermal drift | TCEO | -4 | 4 | µV/°C | 8 | ||
| Gain error | EG | -0.2 | 0.2 | % | TA = 25°C | 8 | |
| Gain error thermal drift | TCEG | -40 | 40 | ppm/°C | 8 | ||
| Differential nonlinearity | DNL | -0.99 | 0.99 | LSB | Resolution: 16 bits | 8 | |
| Integral nonlinearity, differential measurement | INL | -4 | 4 | LSB | Differential measurement; Resolution: 16 bits | 8 | |
| Integral nonlinearity, single-ended measurement | INL | -6 | 6 | LSB | Single-ended measurement; Resolution: 16 bits | 8 | |
| Signal-to-noise ratio | SNR | 80 | 84 | dB | fIN = 1 kHz | 8 | |
| Signal-to-noise + distortion | SINAD | 77 | 84 | dB | fIN = 1 kHz | 8 | |
| Total harmonic distortion | THD | -93 | -80 | dB | VIN = 2 VPP, fIN = 1 kHz | 8 | |
| Spurious-free dynamic range | SFDR | 79 | 96 | dB | VIN = 2 VPP, fIN = 1 kHz | 8 | |
| Low-level input voltage | VIL | -0.3 | V | max is 0.3 × VDD (not numeric) | 8 | ||
| High-level output voltage | VOL | 0.1 | V | IOL = 20 µA | 8 | ||
| Low-level output voltage | VOL | 0.4 | V | IOL = 4 mA | 8 | ||
| Common-mode transient immunity | CMTI | 90 | 150 | kV/μs | 8 | ||
| DC/DC output voltage | VDCDC_OUT | 3.1 | 3.5 | 4.65 | V | DCDC_OUT to HGND | 9 |
| DC/DC output undervoltage detection threshold voltage | VDCDCUV | 2.1 | 2.25 | V | VDCDC_OUT falling | 9 | |
| High-side LDO output voltage | VHLDO_OUT | 3 | 3.2 | 3.4 | V | HLDO_OUT to HGND, up to 1 mA external load | 9 |
| High-side LDO output undervoltage detection threshold voltage | VHLDOUV | 2.4 | 2.6 | V | VHLDO_OUT falling | 9 | |
| High-side supply current for auxiliary circuitry | IH | 1 | mA | Load from HLDOout to HGND; non-switching; -40℃ ≤ TA ≤ 85℃ | 9 | ||
| Low-side supply current | IDD | 28.5 | 42.5 | mA | no external load on HLDO | 9 | |
| Low-side supply current | IDD | 30.5 | 44.5 | mA | 1 mA external load on HLDO | 9 | |
| Device startup time | tSTART | 0.6 | 1.1 | ms | VDD step from 0 to 3.0 V to bitstream valid | 9 | |
| Output load capacitance | CLOAD | 15 | 30 | pF | 8 | ||
| DOUT rise time | tr | 2.5 | 6 | ns | 10% to 90%, 3.0 V ≤ VDD ≤ 3.6 V, CLOAD = 15 pF | 10 | |
| DOUT rise time | tr | 3.2 | 6 | ns | 10% to 90%, 4.5 V ≤ VDD ≤ 5.5 V, CLOAD = 15 pF | 10 | |
| DOUT fall time | tf | 2.2 | 6 | ns | 10% to 90%, 3.0 V ≤ VDD ≤ 3.6 V, CLOAD = 15 pF | 10 | |
| DOUT fall time | tf | 2.9 | 6 | ns | 10% to 90%, 4.5 V ≤ VDD ≤ 5.5 V, CLOAD = 15 pF | 10 | |
| VDD analog undervoltage detection threshold | VDDUV | 2.9 | V | VDD rising | 9 | ||
| VDD digital reset threshold | VDDPOR | 2.5 | V | VDD rising | 9 | ||
| Input current (leakage) | IIN | 7 | μA | GND ≤ VIN ≤ VDD | 8 | ||
| Common-mode rejection ratio | CMRR | -104 | dB | INP = INN, fIN = 0 Hz, VCM min ≤ VCM ≤ VCM max | 8 | ||
| Power-supply rejection ratio | PSRR | -109 | dB | VDD from 3.0 V to 5.5 V, at dc | 8 | ||
| Digital output hold time after rising edge of CLKIN | tH | 3.5 | ns | CLOAD = 15 pF; CLKIN 50% to DOUT 10% / 90% | 10 | ||
| Rising edge of CLKIN to DOUT valid delay | tD | 15 | ns | CLOAD = 15 pF; CLKIN 50% to DOUT 10% / 90% | 10 | ||
| Junction-to-ambient thermal resistance | RθJA | 73.5 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 31 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 44 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ψJT | 16.7 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ψJB | 42.8 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
AMC3336DWER - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
amc3336dwer-etched.step/amc3336dwer-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);amc3336dwer.step/amc3336dwer.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TEXAS INSTRUMENTS datasheet (40 pp, sha256
6ec59953abfa0cd0, retrieved 2026-10-20, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).