component
F280040PMQR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownF280040PMQR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
F280040PMQR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO29 | bidirectional | General-purpose I/O 29 (default GPIO function); also muxed to SCI-A TX, ePWM7B, EQEP1B, LIN-A RX, SPI-B STE and ERRORSTS. |
| 2 | GPIO28 | bidirectional | General-purpose I/O 28 (default GPIO function); also muxed to SCI-A RX, ePWM7A, EQEP1A, LIN-A TX, SPI-B CLK and ERRORSTS. |
| 3 | XRSn | bidirectional | Device reset input and watchdog reset output, open-drain with internal pullup; place a 2.2 kΩ to 10 kΩ resistor between XRSn and VDDIO and at most 100 nF to VSS. |
| 4 | VDD | power_in | 1.2 V digital logic supply; TI recommends a minimum total of about 20 µF decoupling near the VDD pins. |
| 5 | VSS | power_in | Digital ground; must be connected to the board ground. |
| 6 | A6/PGA5_OF | passive | ADC-A analog input 6; also PGA-5 output filter (optional). |
| 7 | B2/C6/PGA3_OF | passive | ADC-B analog input 2 and ADC-C analog input 6; also PGA-3 output filter (optional). |
| 8 | B3/VDAC | passive | ADC-B analog input 3; VDAC is the optional external reference for the on-chip DAC, has an internal 100 pF capacitor to VSSA that cannot be disabled, and needs at least 1 µF if used as DAC reference. |
| 9 | A2/B6/PGA1_OF | passive | ADC-A analog input 2 and ADC-B analog input 6; also PGA-1 output filter (optional). |
| 10 | PGA1_GND/PGA3_GND/PGA5_GND | power_in | Kelvin ground reference for PGA-1, PGA-3 and PGA-5; ideally equal to VSSA. |
| 11 | C4/PGA5_IN | passive | ADC-C analog input 4; PGA-5 amplifier input. |
| 12 | C0/PGA1_IN | passive | ADC-C analog input 0; PGA-1 amplifier input. |
| 13 | C2/PGA3_IN | passive | ADC-C analog input 2; PGA-3 amplifier input. |
| 14 | A1/DACB_OUT | passive | ADC-A analog input 1; also buffered DAC-B output. |
| 15 | A0/B15/C15/DACA_OUT | passive | ADC-A analog input 0 (also ADC-B 15 and ADC-C 15); also buffered DAC-A output. |
| 16 | VREFHIA/VREFHIB/VREFHIC | bidirectional | ADC high reference; driven externally in external reference mode, driven by the device in internal reference mode; place at least 2.2 µF between VREFHIx and VREFLOx close to the device and do not load externally. |
| 17 | VREFLOA/VREFLOB/VREFLOC | input | ADC low reference voltage input for ADC-A, ADC-B and ADC-C. |
| 18 | C1/PGA2_IN | passive | ADC-C analog input 1; PGA-2 amplifier input. |
| 19 | C3/PGA4_IN | passive | ADC-C analog input 3; PGA-4 amplifier input. |
| 20 | PGA2_GND/PGA4_GND/PGA6_GND | power_in | Kelvin ground reference for PGA-2, PGA-4 and PGA-6; ideally equal to VSSA. |
| 21 | VSSA | power_in | Analog ground for the ADC, PGA, CMPSS and DAC circuits. |
| 22 | VDDA | power_in | 3.3 V analog supply; place at least 2.2 µF decoupling to VSSA. |
| 23 | A4/B8/PGA2_OF | passive | ADC-A analog input 4 and ADC-B analog input 8; also PGA-2 output filter (optional). |
| 24 | B4/C8/PGA4_OF | passive | ADC-B analog input 4 and ADC-C analog input 8; also PGA-4 output filter (optional). |
| 25 | A10/B1/C10/PGA7_OF | passive | ADC-A analog input 10, ADC-B analog input 1 and ADC-C analog input 10; also PGA-7 output filter (optional). |
| 26 | VSS | power_in | Digital ground; must be connected to the board ground. |
| 27 | VDD | power_in | 1.2 V digital logic supply; TI recommends a minimum total of about 20 µF decoupling near the VDD pins. |
| 28 | VDDIO | power_in | 3.3 V digital I/O supply; place at least 0.1 µF decoupling on each VDDIO pin. |
| 29 | FLT2 | unconnected | Flash test pin 2, reserved for TI; must be left unconnected (or tied to VSS through 4.7 kΩ or more). |
| 30 | FLT1 | unconnected | Flash test pin 1, reserved for TI; must be left unconnected (or tied to VSS through 4.7 kΩ or more). |
| 31 | GPIO11 | bidirectional | General-purpose I/O 11 (default GPIO function); also muxed to ePWM6B, SCI-B RX, OUTPUTXBAR7, EQEP1B, SPI-A STE and FSIRX-A D1. |
| 32 | GPIO33 | bidirectional | General-purpose I/O 33 (default GPIO function); also muxed to I2C-A SCL (open-drain), SPI-B STE, OUTPUTXBAR4, LIN-A RX, SD1 C3, FSIRX-A CLK and CAN-A RX. |
| 33 | GPIO16 | bidirectional | General-purpose I/O 16 (default GPIO function); also muxed to SPI-A SIMO, CAN-B TX, ePWM5A, SCI-A TX, SD1 D1 and XCLKOUT. |
| 34 | GPIO17 | bidirectional | General-purpose I/O 17 (default GPIO function); also muxed to SPI-A SOMI, CAN-B RX, ePWM5B, SCI-A RX, SD1 C1 and PMBus-A SDA. |
| 35 | GPIO24 | bidirectional | General-purpose I/O 24 (default GPIO function); also muxed to OUTPUTXBAR1, eQEP2A, ePWM8A, SPI-B SIMO, SD1 D1, PMBus-A SCL, SCI-A TX and ERRORSTS. |
| 36 | TCK | input | JTAG test clock input with internal pullup. |
| 37 | GPIO37/TDO | output | JTAG test data output (default function); tri-stated when no JTAG activity, so an internal or external pullup is required to avoid a floating GPIO input. |
| 38 | TMS | bidirectional | JTAG test mode select with internal pullup; datasheet recommends an external 2.2 kΩ pullup to VDDIO on the board. |
| 39 | GPIO35/TDI | input | JTAG test data input (default function); internal pullup is disabled by default, so enable it or add an external pullup to avoid a floating input. |
| 40 | GPIO32 | bidirectional | General-purpose I/O 32 (default GPIO function); also muxed to I2C-A SDA, SPI-B CLK, ePWM8B, LIN-A TX, SD1 D3, FSIRX-A D0 and CAN-A TX. |
| 41 | GPIO18_X2 | bidirectional | GPIO18 (usable only when the system is clocked from INTOSC and X1 has an external pulldown, recommended 1 kΩ) or crystal oscillator output X2; also muxed to SPI-A CLK, SCI-B TX, CAN-A RX, ePWM6A, I2C-A SCL and SD1 D2. |
| 42 | X1 | passive | Crystal oscillator input or single-ended 3.3 V clock input; GPIO19 is internally tied to X1 and must remain an input with pullup disabled. |
| 43 | VDDIO | power_in | 3.3 V digital I/O supply; place at least 0.1 µF decoupling on each VDDIO pin. |
| 44 | VDD | power_in | 1.2 V digital logic supply; TI recommends a minimum total of about 20 µF decoupling near the VDD pins. |
| 45 | VSS | power_in | Digital ground; must be connected to the board ground. |
| 46 | VREGENZ | input | Internal regulator enable with internal pulldown: tie to VSS to enable the internal VREG, or to VDDIO to supply VDD externally. |
| 47 | GPIO8 | bidirectional | General-purpose I/O 8 (default GPIO function); also muxed to ePWM5A, CAN-B TX, ADCSOCAO, eQEP1 STROBE, SCI-A TX, SPI-A SIMO, I2C-A SCL and FSITX-A D1. |
| 48 | GPIO4 | bidirectional | General-purpose I/O 4 (default GPIO function); also muxed to ePWM3A, OUTPUTXBAR3, CAN-A TX and FSIRX-A CLK. |
| 49 | GPIO3 | bidirectional | General-purpose I/O 3 (default GPIO function); also muxed to ePWM2B, OUTPUTXBAR2, PMBus-A SCL, SPI-A CLK, SCI-A RX and FSIRX-A D0. |
| 50 | GPIO2 | bidirectional | General-purpose I/O 2 (default GPIO function); also muxed to ePWM2A, OUTPUTXBAR1, PMBus-A SDA, SCI-A TX and FSIRX-A D1. |
| 51 | GPIO1 | bidirectional | General-purpose I/O 1 (default GPIO function); also muxed to ePWM1B and I2C-A SCL (open-drain). |
| 52 | GPIO0 | bidirectional | General-purpose I/O 0 (default GPIO function); also muxed to ePWM1A and I2C-A SDA (open-drain). |
| 53 | VDDIO_SW | power_in | 3.3 V supply for the internal DC/DC regulator; must be tied to VDDIO, and about 20 µF input capacitance is required when the DC/DC is used. |
| 54 | GPIO23_VSW | bidirectional | GPIO23 by default configured as the DC/DC switch output VSW when DCDCEN=1 (about 100 pF internal capacitance); usable as GPIO23 if the DC/DC is not used. |
| 55 | VSS_SW | power_in | Internal DC/DC regulator ground; must be tied to VSS. |
| 56 | GPIO22_VFBSW | bidirectional | GPIO22 by default configured as DC/DC feedback VFBSW when DCDCEN=1; if the internal DC/DC is used, connect this pin to the node where L(VSW) connects to the VDD rail, close to the device. |
| 57 | GPIO7 | bidirectional | General-purpose I/O 7 (default GPIO function); also muxed to ePWM4B, OUTPUTXBAR5, eQEP1B, CAN-B RX, SPI-B SIMO and FSITX-A CLK. |
| 58 | VSS | power_in | Digital ground; must be connected to the board ground. |
| 59 | VDD | power_in | 1.2 V digital logic supply; TI recommends a minimum total of about 20 µF decoupling near the VDD pins. |
| 60 | VDDIO | power_in | 3.3 V digital I/O supply; place at least 0.1 µF decoupling on each VDDIO pin. |
| 61 | GPIO5 | bidirectional | General-purpose I/O 5 (default GPIO function); also muxed to ePWM3B, OUTPUTXBAR3, CAN-A RX, SPI-A STE and FSITX-A D1. |
| 62 | GPIO9 | bidirectional | General-purpose I/O 9 (default GPIO function); also muxed to ePWM5B, SCI-B TX, OUTPUTXBAR6, eQEP1 INDEX, SCI-A RX, SPI-A CLK and FSITX-A D0. |
| 63 | GPIO10 | bidirectional | General-purpose I/O 10 (default GPIO function); also muxed to ePWM6A, CAN-B RX, ADCSOCBO, eQEP1A, SCI-B TX, SPI-A SOMI, I2C-A SDA and FSITX-A CLK. |
| 64 | GPIO6 | bidirectional | General-purpose I/O 6 (default GPIO function); also muxed to ePWM4A, OUTPUTXBAR4, SYNCOUT, eQEP1A, CAN-B TX, SPI-B SOMI and FSITX-A D0. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
F280040PMQR - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
f280040pmqr-etched.step/f280040pmqr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);f280040pmqr.step/f280040pmqr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (277 pp, sha256
867e7bb5ada6819c, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).