component

74HC20D

Public Made by Adom

by adom

Nexperia Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic74hc20dfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

74HC20D

Nexperia · Logic Gates · SOP-14

74HC20D from Nexperia, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input of NAND gate 1; inputs include clamp diodes, so current-limiting resistors can be used to interface to voltages above VCC.
2 1B input Data input of NAND gate 1; inputs include clamp diodes, so current-limiting resistors can be used to interface to voltages above VCC.
3 n.c. unconnected Not connected.
4 1C input Data input of NAND gate 1; inputs include clamp diodes, so current-limiting resistors can be used to interface to voltages above VCC.
5 1D input Data input of NAND gate 1; inputs include clamp diodes, so current-limiting resistors can be used to interface to voltages above VCC.
6 1Y output Data output of NAND gate 1; output is HIGH if any input is LOW and LOW only when all four inputs are HIGH.
7 GND power_in Ground (0 V) reference for all voltages on the device.
8 2Y output Data output of NAND gate 2; output is HIGH if any input is LOW and LOW only when all four inputs are HIGH.
9 2A input Data input of NAND gate 2; inputs include clamp diodes, so current-limiting resistors can be used to interface to voltages above VCC.
10 2B input Data input of NAND gate 2; inputs include clamp diodes, so current-limiting resistors can be used to interface to voltages above VCC.
11 n.c. unconnected Not connected.
12 2C input Data input of NAND gate 2; inputs include clamp diodes, so current-limiting resistors can be used to interface to voltages above VCC.
13 2D input Data input of NAND gate 2; inputs include clamp diodes, so current-limiting resistors can be used to interface to voltages above VCC.
14 VCC power_in Supply voltage; recommended operating range is 2.0 V to 6.0 V referenced to GND.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 2 5 6 V 4
ambient temperature Tamb -40 25 125 °C 4
input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 4
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 4
supply voltage VCC -0.5 7 V 3
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V [1] 3
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V [1] 3
output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 3
supply current ICC 50 mA 3
ground current IGND -50 mA 3
storage temperature Tstg -65 150 °C 3
total power dissipation Ptot 500 mW 3
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V 4
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V 4
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V 4
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V 4
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V 4
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V 4
HIGH-level output voltage VOH 1.9 2 V IO = -20 μA; VCC = 2.0 V 4
HIGH-level output voltage VOH 4.4 4.5 V IO = -20 μA; VCC = 4.5 V 4
HIGH-level output voltage VOH 5.9 6 V IO = -20 μA; VCC = 6.0 V 4
HIGH-level output voltage VOH 3.7 4.32 V IO = -4.0 mA; VCC = 4.5 V 4
HIGH-level output voltage VOH 5.2 5.81 V IO = -5.2 mA; VCC = 6.0 V 4
LOW-level output voltage VOL 0 0.1 V IO = 20 μA; VCC = 2.0 V 4
LOW-level output voltage VOL 0.15 0.4 V IO = 4.0 mA; VCC = 4.5 V 4
LOW-level output voltage VOL 0.16 0.4 V IO = 5.2 mA; VCC = 6.0 V 4
input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V 4
supply current ICC 40 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V 4
propagation delay tpd 28 135 ns nA, nB, nC, nD to nY; see Fig. 7; VCC = 2.0 V 5
propagation delay tpd 10 27 ns nA, nB, nC, nD to nY; see Fig. 7; VCC = 4.5 V 5
propagation delay tpd 8 23 ns nA, nB, nC, nD to nY; see Fig. 7; VCC = 6.0 V 5
transition time tt 19 110 ns nY; see Fig. 7; VCC = 2.0 V 5
transition time tt 7 22 ns nY; see Fig. 7; VCC = 4.5 V 5
transition time tt 6 19 ns nY; see Fig. 7; VCC = 6.0 V 5

CAD (KiCad official)

  • Symbol: 74HC20D
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74hc20d-etched.step / 74hc20d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc20d.step / 74hc20d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (11 pp, sha256 4465f31709c3a9a0, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF