component
CA-IS3841HW
Public Made by Adomby adom
Chipanalog Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCA-IS3841HW
Chipanalog · Digital Isolators · SOIC-16-300mil
CA-IS3841HW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | A-side supply voltage, recommended 2.375 V to 5.5 V; the datasheet calls for a 0.1 µF to 1 µF bypass capacitor placed within 2 mm of the pin. |
| 2 | GNDA | power_in | A-side ground reference point for the input-side supply and logic. |
| 3 | VI1 | input | A-side logic input of forward channel 1; accepts CMOS and TTL levels and sinks only microampere-level leakage. |
| 4 | VI2 | input | A-side logic input of forward channel 2; accepts CMOS and TTL levels and sinks only microampere-level leakage. |
| 5 | VI3 | input | A-side logic input of forward channel 3 on the CA-IS3841 (pin shared with VO3 on other variants); accepts CMOS and TTL levels. |
| 6 | VO4 | output | A-side logic output of the reverse channel 4 on the CA-IS3841; push-pull output with about 50 Ω output impedance, high-Z when ENA is low. |
| 7 | ENA | input | A-side enable input, active high or floating (internally pulled up to local VDD); drive it to a defined logic level in noisy environments and keep traces off it if left floating. |
| 8 | GNDA | power_in | A-side ground reference point for the input-side supply and logic. |
| 9 | GNDB | power_in | B-side ground reference point for the output-side supply and logic. |
| 10 | ENB | input | B-side enable input, active high or floating (internally pulled up to local VDD); when low, outputs VO1 to VO3 go high-impedance. |
| 11 | VI4 | input | B-side logic input of reverse channel 4 on the CA-IS3841 (pin shared with VO4 on other variants); accepts CMOS and TTL levels. |
| 12 | VO3 | output | B-side logic output of forward channel 3 on the CA-IS3841 (pin shared with VI3 on other variants); push-pull output with about 50 Ω output impedance. |
| 13 | VO2 | output | B-side logic output of forward channel 2; push-pull output with about 50 Ω output impedance, high-Z when ENB is low. |
| 14 | VO1 | output | B-side logic output of forward channel 1; push-pull output with about 50 Ω output impedance, high-Z when ENB is low. |
| 15 | GNDB | power_in | B-side ground reference point for the output-side supply and logic. |
| 16 | VDDB | power_in | B-side supply voltage, recommended 2.375 V to 5.5 V; the datasheet calls for a 0.1 µF to 1 µF bypass capacitor placed within 2 mm of the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16-300mil |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDDA, VDDB supply voltage | VDDA, VDDB | 2.375 | 5.5 | V | 5 | ||
| VDD rising UVLO threshold | VDD（UVLO+） | 1.95 | 2.24 | 2.375 | V | 5 | |
| VDD falling UVLO threshold | VDD（UVLO-） | 1.88 | 2.1 | 2.325 | V | 5 | |
| UVLO hysteresis | VHYS（UVLO） | 70 | 140 | 250 | mV | 5 | |
| High-level output current | IOH | -4 | mA | VDDO1 = 5V | 5 | ||
| High-level output current | IOH | -2 | mA | VDDO = 3.3V | 5 | ||
| High-level output current | IOH | -1 | mA | VDDO = 2.5V | 5 | ||
| Low-level output current | IOL | 4 | mA | VDDO = 5V | 5 | ||
| Low-level output current | IOL | 2 | mA | VDDO = 3.3V | 5 | ||
| Low-level output current | IOL | 1 | mA | VDDO = 2.5V | 5 | ||
| Input threshold logic high | VIH | 2 | V | 5 | |||
| Input threshold logic low | VIL | 0.8 | V | 5 | |||
| Signal data rate | DR | 0 | 150 | Mbps | 5 | ||
| Ambient temperature | TA | -40 | 27 | 125 | °C | 5 | |
| Supply voltage VDDA, VDDB (absolute maximum) | VDDA, VDDB | -0.5 | 6 | V | 5 | ||
| Input voltage Ax, Bx, ENx (absolute maximum; printed max VDDA+0.5, see review) | Vin | -0.5 | V | 5 | |||
| Output current | IO | -20 | 20 | mA | 5 | ||
| Junction temperature | TJ | 150 | °C | 5 | |||
| Storage temperature range | TSTG | -65 | 150 | °C | 5 | ||
| ESD human body model | VESD | -8000 | 8000 | V | HBM, all pins, ANSI/ESDA/JEDEC JS-001 | 5 | |
| ESD charged device model | VESD | -2000 | 2000 | V | CDM, all pins, JESD22-C101 | 5 | |
| Maximum power dissipation (CA-IS3841) | PD | 334 | mW | VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, input 75-MHz 50% duty square wave | 6 | ||
| Maximum power dissipation, side A (CA-IS3841) | PDA | 100 | mW | VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, input 75-MHz 50% duty square wave | 6 | ||
| Maximum power dissipation, side B (CA-IS3841) | PDB | 234 | mW | VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, input 75-MHz 50% duty square wave | 6 | ||
| Input threshold logic high, Ax/Bx (5 V) | VIT+(IN) | 2 | V | 9 | |||
| Input threshold logic low, Ax/Bx (5 V) | VIT-(IN) | 0.8 | V | 9 | |||
| Output voltage logic low (5 V) | VOL | 0.2 | 0.4 | V | IOL = 4mA; 图 8-2 | 9 | |
| Input high leakage current (5 V) | IIH | 20 | µA | VIH = VDDA at Ax or Bx or ENx | 9 | ||
| Input low leakage current (5 V) | IIL | -20 | µA | VIL = 0 V at Ax or Bx | 9 | ||
| Common-mode transient immunity (5 V) | CMTI | 100 | 150 | kV/µs | VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-4 | 9 | |
| Disable-state supply current IDDA, ENA=ENB=0 V, VIN=0 V (L) / VDDI (H) (5 V) | IDDA | 1.5 | 2.4 | mA | ENA = ENB = 0 V; VIN = 0V (CA-IS3841L); VIN = VDDI (CA-IS3841H) | 10 | |
| Disable-state supply current IDDB, ENA=ENB=0 V, VIN=0 V (L) / VDDI (H) (5 V) | IDDB | 2.3 | 3.6 | mA | ENA = ENB = 0 V; VIN = 0V (CA-IS3841L); VIN = VDDI (CA-IS3841H) | 10 | |
| Disable-state supply current IDDA, ENA=ENB=0 V, VIN=VDDI (L) / 0 V (H) (5 V) | IDDA | 4.1 | 6.8 | mA | ENA = ENB = 0 V; VIN = VDDI (CA-IS3841L); VIN = 0V(CA-IS3841H) | 10 | |
| Disable-state supply current IDDB, ENA=ENB=0 V, VIN=VDDI (L) / 0 V (H) (5 V) | IDDB | 3.2 | 5.1 | mA | ENA = ENB = 0 V; VIN = VDDI (CA-IS3841L); VIN = 0V(CA-IS3841H) | 10 | |
| DC-signal supply current IDDA, ENA=ENB=VDDI, VIN=0 V (L) / VDDI (H) (5 V) | IDDA | 1.6 | 2.5 | mA | ENA = ENB = VDDI; VIN = 0V (CA-IS3841L); VIN = VDDI (CA-IS3841H) | 10 | |
| DC-signal supply current IDDB, ENA=ENB=VDDI, VIN=0 V (L) / VDDI (H) (5 V) | IDDB | 2.5 | 3.9 | mA | ENA = ENB = VDDI; VIN = 0V (CA-IS3841L); VIN = VDDI (CA-IS3841H) | 10 | |
| DC-signal supply current IDDA, ENA=ENB=VDDI, VIN=VDDI (L) / 0 V (H) (5 V) | IDDA | 4.2 | 6.9 | mA | ENA = ENB = VDDI; VIN = VDDI (CA-IS3841L); VIN = 0V(CA-IS3841H) | 10 | |
| DC-signal supply current IDDB, ENA=ENB=VDDI, VIN=VDDI (L) / 0 V (H) (5 V) | IDDB | 3.5 | 5.4 | mA | ENA = ENB = VDDI; VIN = VDDI (CA-IS3841L); VIN = 0V(CA-IS3841H) | 10 | |
| AC-signal supply current IDDA at 1 Mbps (5 V) | IDDA | 3.3 | 5.2 | mA | ENA = ENB = VDDI; all channels 50% duty 5 V square wave; CL = 15 pF; 1Mbps (500kHz) | 10 | |
| AC-signal supply current IDDB at 1 Mbps (5 V) | IDDB | 4.1 | 6.2 | mA | ENA = ENB = VDDI; all channels 50% duty 5 V square wave; CL = 15 pF; 1Mbps (500kHz) | 10 | |
| AC-signal supply current IDDA at 10 Mbps (5 V) | IDDA | 6.9 | 9.9 | mA | ENA = ENB = VDDI; all channels 50% duty 5 V square wave; CL = 15 pF; 10Mbps (5MHz) | 10 | |
| AC-signal supply current IDDB at 10 Mbps (5 V) | IDDB | 14 | 19.5 | mA | ENA = ENB = VDDI; all channels 50% duty 5 V square wave; CL = 15 pF; 10Mbps (5MHz) | 10 | |
| AC-signal supply current IDDA at 100 Mbps (5 V) | IDDA | 14.3 | 19.8 | mA | ENA = ENB = VDDI; all channels 50% duty 5 V square wave; CL = 15 pF; 100Mbps (50MHz) | 10 | |
| AC-signal supply current IDDB at 100 Mbps (5 V) | IDDB | 32.5 | 44 | mA | ENA = ENB = VDDI; all channels 50% duty 5 V square wave; CL = 15 pF; 100Mbps (50MHz) | 10 | |
| Minimum pulse width (5 V) | PWmin | 5 | ns | 13 | |||
| Propagation delay (5 V) | tPLH, tPHL | 12 | 15 | ns | 图 8-1 | 13 | |
| Pulse width distortion (5 V) | PWD | 0.2 | 4.5 | ns | /tPLH - tPHL/ | 13 | |
| Channel-to-channel output skew, same direction (5 V) | tsk(o) | 0.4 | 2.5 | ns | 同方向通道 | 13 | |
| Part-to-part channel output skew (5 V) | tsk(pp) | 2 | 4.5 | ns | 13 | ||
| Output rise time (5 V) | tr | 2.5 | 4 | ns | 图 8-1 | 13 | |
| Output fall time (5 V) | tf | 2.5 | 4 | ns | 图 8-1 | 13 | |
| Disable propagation delay, output high to high-Z (5 V) | tPHZ | 12 | 20 | ns | 图 8-2 | 13 | |
| Disable propagation delay, output low to high-Z (5 V) | tPLZ | 12 | 20 | ns | 13 | ||
| Enable propagation delay, output high-Z to high (5 V) | tPZH | 15 | 25 | ns | 13 | ||
| Enable propagation delay, output high-Z to low (5 V) | tPZL | 15 | 25 | ns | 13 | ||
| Default output delay from input supply reaching UVLO (5 V) | tDO | 8 | 12 | µs | 图 8-3 | 13 | |
| Start-up time (5 V) | tSU | 15 | 40 | µs | 13 | ||
| High-level output voltage (5 V) | VOH | 4.8 | V | IOH = -4mA; 图 8-2 | 9 | ||
| Thermal resistance, junction to ambient (SOIC16-WB) | RθJA | 83.4 | °C/W | 6 |
CAD (KiCad official)
- Symbol:
CA-IS3841HW - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
ca-is3841hw-etched.step/ca-is3841hw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3841hw.step/ca-is3841hw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (24 pp, sha256
9db82420343a3e86, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).