component
TF2104M-TAH
Public Made by Adomby adom
TFSS Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTF2104M-TAH
TFSS · Gate Drive ICs · SOIC-8
TF2104M-TAH from TFSS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Logic and low side supply, recommended 10V to 20V. |
| 2 | IN | input | Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO, with 3.3V logic capability and a recommended 0V to 5V input range. |
| 3 | SD* | input | Logic input for shutdown, enabled low. |
| 4 | COM | power_in | Low-side and logic return. |
| 5 | LO | output | Low-side gate drive output. |
| 6 | VS | power_in | High-side floating supply return, with offset up to 600V. |
| 7 | HO | output | High-side gate drive output. |
| 8 | VB | power_in | High-side floating supply, recommended VS + 10V to VS + 20V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TFSS |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High side floating supply absolute voltage (VCC supply range, low side) | VCC | 10 | 20 | V | 3 | ||
| Logic input voltage (IN and SD*) | VIN | 0 | 5 | V | 3 | ||
| Ambient temperature | TA | -40 | 125 | °C | 3 | ||
| Low side output voltage | VLO | 0 | V | 3 | |||
| High side floating supply offset voltage | VS | 600 | V | NOTE3: logic operational for VS of -5V to +600V | 3 | ||
| Input pulse amplitude (IN and SD*) for optimal operation | 2.5 | V | NOTE5: recommended for optimal operation | 4 | |||
| Input pulse width (IN and SD*) for optimal operation | 840 | ns | NOTE5: recommended for optimal operation | 4 | |||
| VB - High side floating supply voltage | VB | -0.3 | 624 | V | 3 | ||
| Offset supply voltage transient | dVS/dt | 50 | V/ns | 3 | |||
| VCC - Low-side fixed supply voltage | VCC | -0.3 | 24 | V | 3 | ||
| Low-side output voltage | VLO | -0.3 | V | 3 | |||
| Logic input voltage (IN and SD*) | VIN | -0.3 | V | 3 | |||
| Junction operating temperature | TJ | 150 | °C | 3 | |||
| Lead temperature (soldering) | TL | 300 | °C | soldering, 10 seconds | 3 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 3 | ||
| Logic '1' (IN) & Logic '0' (SD*) input voltage | VIH | 2.5 | V | VCC= 10V to 20V | 4 | ||
| Logic '0' (IN) & Logic '1' (SD*) input voltage | VIL | 0.8 | V | 4 | |||
| High level output voltage, VBIAS - VO | VOH | 0.05 | 0.2 | V | IO = 2mA | 4 | |
| Low level output voltage, VO | VOL | 0.02 | 0.1 | V | IO = 2mA | 4 | |
| Offset supply leakage current | ILK | 50 | mA | VB = VS = 600V | 4 | ||
| Quiescent VBS supply current | IBSQ | 60 | 100 | mA | VIN = 0V or 5V | 4 | |
| Quiescent VCC supply current | ICCQ1 | 350 | 500 | mA | IN=0V or 5V, SD*=5V | 4 | |
| Quiescent VCC supply current in shutdown | ICCQ2 | 590 | 750 | mA | IN=0V or 5V, SD*=0V | 4 | |
| Logic '1' input bias current | IIN+ | 3 | 10 | mA | IN = 5V, SD* = 0V | 4 | |
| Logic '0' input bias current | IIN- | 5 | mA | IN = 0V, SD* = 5V | 4 | ||
| VCC supply under-voltage positive going threshold | VCCUV+ | 8 | 8.9 | 9.8 | V | 4 | |
| VCC supply under-voltage negative going threshold | VCCUV- | 7.4 | 8.2 | 9 | V | 4 | |
| VBS supply under-voltage positive going threshold | VBSUV+ | 4.5 | 5.5 | 6.5 | V | 4 | |
| VBS supply under-voltage negative going threshold | VBSUV- | 4.2 | 5.2 | 6.2 | V | 4 | |
| Output high short circuit pulsed current | IO+ | 130 | 290 | mA | VO = 0V, PW ≤ 10 ms | 4 | |
| Output low short circuit pulsed current | IO- | 270 | 600 | mA | VO = 15V, PW ≤ 10 ms | 4 | |
| Turn-on propagation delay | ton | 680 | 820 | ns | VS = 0V | 5 | |
| Turn-off propagation delay | toff | 150 | 220 | ns | VS = 600V | 5 | |
| Shutdown propagation delay | tSD | 160 | 220 | ns | 5 | ||
| Delay matching, HS & LS turn-on/turn-off | tDM | 60 | ns | 5 | |||
| Turn-on rise time | tr | 70 | 170 | ns | VS = 0V | 5 | |
| Turn-off fall time | tf | 35 | 90 | ns | 5 | ||
| Deadtime: tDT LO-HO & tDT HO-LO | tDT | 300 | 420 | 650 | ns | 5 |
CAD (KiCad official)
- Symbol:
TF2104M-TAH - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tf2104m-tah-etched.step/tf2104m-tah-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tf2104m-tah.step/tf2104m-tah.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TFSS datasheet (9 pp, sha256
c44ac411bba323cb, retrieved 2026-11-04, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).