component
LM3940IT-3.3
Public Made by Adomby adom
Texas Instruments Linear Voltage Regulators (LDO), TO-220. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Contents
README
markdownLM3940IT-3.3
Texas Instruments · Linear Voltage Regulators (LDO) · TO-220
LM3940IT-3.3 from Texas Instruments, in a TO-220. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input voltage supply (4.5 V to 5.5 V recommended); a 0.47-µF capacitor should be connected at this input. |
| 2 | GND | power_in | Common ground. |
| 3 | OUT | power_out | Regulated 3.3-V output, up to 1 A; a 33-µF low ESR capacitor should be connected to this pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TO-220 |
| Category | Power Supply Chip |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage | VOUT | 3.2 | 3.3 | 3.4 | V | 5 mA ≤ IOUT ≤ 1 A, TJ = 25°C | 5 |
| Output voltage | VOUT | 3.13 | 3.47 | V | 5 mA ≤ IOUT ≤ 1 A, -40°C ≤ TJ ≤ 125°C | 5 | |
| Line regulation | 20 | 40 | mV | IOUT = 5 mA, 4.5 V ≤ VIN ≤ 5.5 V | 5 | ||
| Load regulation | 35 | 50 | mV | 50 mA ≤ IOUT ≤ 1 A, TJ = 25°C | 5 | ||
| Load regulation | 35 | 80 | mV | 50 mA ≤ IOUT ≤ 1 A, -40°C ≤ TJ ≤ 125°C | 5 | ||
| Quiescent current | IQ | 10 | 15 | mA | 4.5 V ≤ VIN ≤ 5.5 V, IOUT = 5 mA, TJ = 25°C | 5 | |
| Quiescent current | IQ | 10 | 20 | mA | 4.5 V ≤ VIN ≤ 5.5 V, IOUT = 5 mA, -40°C ≤ TJ ≤ 125°C | 5 | |
| Quiescent current | IQ | 110 | 200 | mA | VIN = 5 V, IOUT = 1 A, TJ = 25°C | 5 | |
| Quiescent current | IQ | 110 | 250 | mA | VIN = 5 V, IOUT = 1 A, -40°C ≤ TJ ≤ 125°C | 5 | |
| Dropout voltage | VDO | 0.5 | 0.8 | V | IOUT = 1 A, TJ = 25°C | 5 | |
| Dropout voltage | VDO | 0.5 | 1 | V | IOUT = 1 A, -40°C ≤ TJ ≤ 125°C | 5 | |
| Dropout voltage | VDO | 110 | 150 | mV | IOUT = 100 mA, TJ = 25°C | 5 | |
| Dropout voltage | VDO | 110 | 200 | mV | IOUT = 100 mA, -40°C ≤ TJ ≤ 125°C | 5 | |
| Short-circuit current | IOUT(SC) | 1.2 | 1.7 | A | RL = 0 | 5 | |
| Output impedance | ZOUT | 35 | mΩ | IOUT (DC) = 100 mA, IOUT (AC) = 20 mA (rms), ƒ = 120 Hz | 5 | ||
| Output noise voltage | en | 150 | μV(rms) | ƒBW = 10 Hz, 100 kHz, IOUT = 5 mA | 5 | ||
| Input supply voltage | VIN | -0.3 | 7.5 | V | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 | 4 | |
| ESD CDM | V(ESD) | -500 | 500 | V | Charged-device model (CDM), per JEDEC specification JESD22-C101 | 4 | |
| Junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Input supply voltage | VIN | 4.5 | 5.5 | V | 4 | ||
| Junction-to-ambient thermal resistance, High-K | RθJA | 23.3 | °C/W | TO-220 (NDE) | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 16.1 | °C/W | TO-220 (NDE) | 4 | ||
| Junction-to-board thermal resistance | RθJB | 4.8 | °C/W | TO-220 (NDE) | 4 | ||
| Junction-to-top characterization parameter | ψJT | 2.7 | °C/W | TO-220 (NDE) | 4 | ||
| Junction-to-board characterization parameter | ψJB | 4.8 | °C/W | TO-220 (NDE) | 4 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 1.1 | °C/W | TO-220 (NDE) | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is stron | 11 |
CAD (KiCad official)
- Symbol:
LM3940IT-3.3 - Footprint:
Package_TO_SOT_THT:TO-220-3_Vertical - 3D model: TO-220 (KiCad packages3D, STEP)
- 3D model files:
lm3940it-3-3-etched.step/lm3940it-3-3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm3940it-3-3.step/lm3940it-3-3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
88a74e653c540072, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).