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74HC73D

Public Made by Adom

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Nexperia Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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74HC73D

Nexperia · Flip Flops · SOIC-14

74HC73D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CP input Clock input of flip-flop 1, triggered on the HIGH-to-LOW transition, with Schmitt-trigger action that tolerates slow clock edges; input voltage range is 0 V to VCC.
2 ~{1R} input Asynchronous active-LOW reset of flip-flop 1; when LOW it overrides the clock and data inputs, forcing 1Q LOW and 1~{Q} HIGH.
3 1K input Synchronous K data input of flip-flop 1, which must be stable one set-up time before the HIGH-to-LOW clock transition.
4 VCC power_in Positive supply voltage; recommended operating range is 2.0 V to 6.0 V with an absolute maximum of 7.0 V.
5 2CP input Clock input of flip-flop 2, triggered on the HIGH-to-LOW transition, with Schmitt-trigger action that tolerates slow clock edges; input voltage range is 0 V to VCC.
6 ~{2R} input Asynchronous active-LOW reset of flip-flop 2; when LOW it overrides the clock and data inputs, forcing 2Q LOW and 2~{Q} HIGH.
7 2J input Synchronous J data input of flip-flop 2, which must be stable one set-up time before the HIGH-to-LOW clock transition.
8 ~{2Q} output Complement output of flip-flop 2, the inverse of 2Q.
9 2Q output True output of flip-flop 2.
10 2K input Synchronous K data input of flip-flop 2, which must be stable one set-up time before the HIGH-to-LOW clock transition.
11 GND power_in Ground reference, 0 V.
12 1Q output True output of flip-flop 1.
13 ~{1Q} output Complement output of flip-flop 1, the inverse of 1Q.
14 1J input Synchronous J data input of flip-flop 1, which must be stable one set-up time before the HIGH-to-LOW clock transition.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 4
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
Output current IO -25 25 mA VO = -0.5 V to VCC + 0.5 V 4
Supply current ICC 50 mA 4
Ground current IGND -50 mA 4
Storage temperature Tstg -65 150 °C 4
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
Supply voltage VCC 2 5 6 V 4
Input voltage VI 0 V maximum printed as VCC 4
Output voltage VO 0 V maximum printed as VCC 4
Ambient temperature Tamb -40 125 °C 4
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 4
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 4
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V 4
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V 4
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V 4
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V 4
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V 4
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V 4
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V 5
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V 5
HIGH-level output voltage VOH 5.9 6 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V 5
HIGH-level output voltage VOH 3.7 4.32 V VI = VIH or VIL; IO = -4 mA; VCC = 4.5 V 5
HIGH-level output voltage VOH 5.2 5.81 V VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V 5
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V 5
LOW-level output voltage VOL 0.15 0.4 V VI = VIH or VIL; IO = 4 mA; VCC = 4.5 V 5
LOW-level output voltage VOL 0.16 0.4 V VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V 5
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V 5
Supply current ICC 80 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V 5
Propagation delay nCP to nQ tpd 52 240 ns CL = 50 pF; VCC = 2.0 V; see Fig. 7 5
Propagation delay nCP to nQ tpd 19 48 ns CL = 50 pF; VCC = 4.5 V; see Fig. 7 5
Propagation delay nCP to nQ tpd 15 41 ns CL = 50 pF; VCC = 6.0 V; see Fig. 7 5
Propagation delay nR to nQ, nQ tpd 50 220 ns CL = 50 pF; VCC = 2.0 V; see Fig. 8 5
Propagation delay nR to nQ, nQ tpd 18 44 ns CL = 50 pF; VCC = 4.5 V; see Fig. 8 5
Propagation delay nR to nQ, nQ tpd 14 38 ns CL = 50 pF; VCC = 6.0 V; see Fig. 8 5
Transition time nQ, nQ tt 19 110 ns CL = 50 pF; VCC = 2.0 V; see Fig. 7 6
Transition time nQ, nQ tt 7 22 ns CL = 50 pF; VCC = 4.5 V; see Fig. 7 6
Transition time nQ, nQ tt 6 19 ns CL = 50 pF; VCC = 6.0 V; see Fig. 7 6
Pulse width nCP input HIGH or LOW tW 120 22 ns VCC = 2.0 V; see Fig. 7 6
Pulse width nCP input HIGH or LOW tW 24 8 ns VCC = 4.5 V; see Fig. 7 6
Pulse width nCP input HIGH or LOW tW 20 6 ns VCC = 6.0 V; see Fig. 7 6
Pulse width nR input HIGH or LOW tW 120 22 ns VCC = 2.0 V; see Fig. 8 6
Pulse width nR input HIGH or LOW tW 24 8 ns VCC = 4.5 V; see Fig. 8 6
Pulse width nR input HIGH or LOW tW 20 6 ns VCC = 6.0 V; see Fig. 8 6
Recovery time nR to nCP trec 120 22 ns VCC = 2.0 V; see Fig. 8 6
Recovery time nR to nCP trec 24 8 ns VCC = 4.5 V; see Fig. 8 6
Recovery time nR to nCP trec 20 6 ns VCC = 6.0 V; see Fig. 8 6
Set-up time nJ, nK to nCP tsu 120 22 ns VCC = 2.0 V; see Fig. 7 6
Set-up time nJ, nK to nCP tsu 24 8 ns VCC = 4.5 V; see Fig. 7 6
Set-up time nJ, nK to nCP tsu 20 6 ns VCC = 6.0 V; see Fig. 7 6
Hold time nJ, nK to nCP th 3 -8 ns VCC = 2.0 V; see Fig. 7 6
Hold time nJ, nK to nCP th 3 -3 ns VCC = 4.5 V; see Fig. 7 6
Hold time nJ, nK to nCP th 3 -2 ns VCC = 6.0 V; see Fig. 7 6
Maximum clock frequency nCP input fmax 4 23 MHz VCC = 2.0 V; see Fig. 7 6
Maximum clock frequency nCP input fmax 20 70 MHz VCC = 4.5 V; see Fig. 7 6
Maximum clock frequency nCP input fmax 24 83 MHz VCC = 6.0 V; see Fig. 7 6

CAD (KiCad official)

  • Symbol: 74HC73D
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: 74hc73d-etched.step / 74hc73d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc73d.step / 74hc73d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (13 pp, sha256 fa0accacf327f8fa, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF