AD9748ACPZ from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DB1	input	Data bit 1 of the 8-bit CMOS-compatible digital input word, referenced to DCOM and supporting 3 V CMOS logic families.
2	DB0	input	Least significant data bit (LSB) of the 8-bit CMOS-compatible digital input word, referenced to DCOM and supporting 3 V CMOS logic families.
3	DVDD	power_in	Digital supply voltage, specified at 3.3 V nominal with a 2.7 V to 3.6 V supply range.
4	NC	unconnected	No internal connection; do not connect to this pin.
5	NC	unconnected	No internal connection; do not connect to this pin.
6	NC	unconnected	No internal connection; do not connect to this pin.
7	NC	unconnected	No internal connection; do not connect to this pin.
8	NC	unconnected	No internal connection; do not connect to this pin.
9	NC	unconnected	No internal connection; do not connect to this pin.
10	DCOM	power_in	Digital common (ground) return for the digital supply DVDD and digital inputs.
11	CLKVDD	power_in	Clock supply voltage, specified at 3.3 V nominal with a 2.7 V to 3.6 V supply range.
12	CLK+	input	Differential clock input (positive); supports LVPECL or CMOS clock input and up to 210 MSPS conversion rate.
13	CLK-	input	Differential clock input (negative); float this pin for single-ended CMOS drive on CLK+ or for PECL receiver operation.
14	CLKCOM	power_in	Clock common (ground) return for the clock receiver circuitry.
15	CMODE	input	Clock mode select: connect to CLKCOM for single-ended, to CLKVDD for differential, or float for PECL receiver with on-chip terminations.
16	MODE	input	Input data format select: connect to DCOM for straight binary coding or to DVDD for twos complement coding.
17	AVDD	power_in	Analog supply voltage, specified at 3.3 V nominal with a 2.7 V to 3.6 V supply range.
18	AVDD	power_in	Analog supply voltage, specified at 3.3 V nominal with a 2.7 V to 3.6 V supply range.
19	ACOM	power_in	Analog common (ground) return for the DAC current source array and analog supply AVDD.
20	IOUTB	output	Complementary DAC current output, carrying full-scale current when all data bits are 0s; compliance range is -1.0 V to +1.25 V.
21	IOUTA	output	DAC current output, carrying full-scale current when all data bits are 1s; compliance range is -1.0 V to +1.25 V.
22	ACOM	power_in	Analog common (ground) return for the DAC current source array and analog supply AVDD.
23	REFIO	bidirectional	Reference input/output; requires a 0.1 µF capacitor to ACOM.
24	FS ADJ	passive	Full-scale current output adjust, which sets the DAC full-scale current (2 mA to 20 mA).
25	SLEEP	input	Active-high power-down control input with an internal pull-down, so it can be left unterminated if not used.
26	DCOM	power_in	Digital common (ground) return for the digital supply DVDD and digital inputs.
27	DB7	input	Most significant data bit (MSB) of the 8-bit CMOS-compatible digital input word, referenced to DCOM.
28	DB6	input	Data bit 6 of the 8-bit CMOS-compatible digital input word, referenced to DCOM.
29	DB5	input	Data bit 5 of the 8-bit CMOS-compatible digital input word, referenced to DCOM.
30	DB4	input	Data bit 4 of the 8-bit CMOS-compatible digital input word, referenced to DCOM.
31	DB3	input	Data bit 3 of the 8-bit CMOS-compatible digital input word, referenced to DCOM.
32	DB2	input	Data bit 2 of the 8-bit CMOS-compatible digital input word, referenced to DCOM.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-32(5x5)
Category	Interface ICs
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Integral Linearity Error (INL)	INL	-0.25	0.1	0.25	LSB	Measured at IOUTA, driving a virtual ground	3
Differential Nonlinearity (DNL)	DNL	-0.25	0.1	0.25	LSB	Measured at IOUTA, driving a virtual ground	3
Offset Error		-0.02		0.02	% of FSR		3
Gain Error (Without Internal Reference)		-0.5	0.1	0.5	% of FSR		3
Gain Error (With Internal Reference)		-0.5	0.1	0.5	% of FSR		3
Full-Scale Output Current	IOUTFS	2		20	mA		3
Output Compliance Range		-1		1.25	V		3
Reference Voltage		1.14	1.2	1.26	V		3
Reference Input Compliance Range		0.1		1.25	V		3
Gain Drift (Without Internal Reference)		-50		50	ppm of FSR/°C		3
Gain Drift (With Internal Reference)		-100		100	ppm of FSR/°C		3
Reference Voltage Drift		-50		50	ppm/°C		3
AVDD Supply Voltage	AVDD	2.7	3.3	3.6	V		3
DVDD Supply Voltage	DVDD	2.7	3.3	3.6	V		3
CLKVDD Supply Voltage	CLKVDD	2.7	3.3	3.6	V		3
Analog Supply Current	IAVDD		33	36	mA		3
Digital Supply Current	IDVDD		8	9	mA	Measured at fCLOCK = 100 MSPS and fOUT = 1 MHz	3
Clock Supply Current	ICLKVDD		5	7	mA		3
Supply Current Sleep Mode	IAVDD		5	6	mA		3
Power Dissipation	PD		135	145	mW	Measured at fCLOCK = 100 MSPS and fOUT = 1 MHz	3
Power Supply Rejection Ratio, AVDD	PSRR	-1		1	% of FSR/V	±5% power supply variation	3
Power Supply Rejection Ratio, DVDD	PSRR	-0.04		0.04	% of FSR/V	±5% power supply variation	3
Operating Range		-40		85	°C		3
Logic 1 Voltage	VIH	2.1		3	V		5
Logic 0 Voltage	VIL	0		0.9	V		5
Logic 1 Current	IIH	-10		10	μA		5
Logic 0 Current	IIL	-10		10	μA		5
CLK Input Voltage Range		0		3	V		5
CLK Common-Mode Voltage		0.75	1.5	2.25	V		5
CLK Differential Voltage		0.5		1.5	V		5
AVDD with respect to ACOM	AVDD	-0.3		3.9	V		6
DVDD with respect to DCOM	DVDD	-0.3		3.9	V		6
CLKVDD with respect to CLKCOM	CLKVDD	-0.3		3.9	V		6
ACOM with respect to DCOM		-0.3		0.3	V		6
ACOM with respect to CLKCOM		-0.3		0.3	V		6
DCOM with respect to CLKCOM		-0.3		0.3	V		6
AVDD with respect to DVDD		-3.9		3.9	V		6
AVDD with respect to CLKVDD		-3.9		3.9	V		6
DVDD with respect to CLKVDD		-3.9		3.9	V		6
CLK+, CLK−, SLEEP with respect to DCOM		-0.3			V	Maximum is DVDD + 0.3 V	6
Digital Inputs, MODE with respect to DCOM		-0.3			V	Maximum is DVDD + 0.3 V	6
IOUTA, IOUTB with respect to ACOM		-1			V	Maximum is AVDD + 0.3 V	6
REFIO, FS ADJ with respect to ACOM		-0.3			V	Maximum is AVDD + 0.3 V	6
CLK+, CLK−, MODE with respect to CLKCOM		-0.3			V	Maximum is CLKVDD + 0.3 V	6
Junction Temperature	TJ			150	°C		6
Storage Temperature Range	TSTG	-65		150	°C		6
Output Resistance	ROUT		100		kΩ		3
Output Capacitance	COUT		5		pF		3
Reference Output Current			100		nA		3
Reference Input Resistance (External Reference)			7		kΩ		3
Small Signal Bandwidth			0.5		MHz		3
Offset Drift			0		ppm of FSR/°C		3
Maximum Output Update Rate	fCLOCK		210		MSPS		4
Output Settling Time	tST		11		ns	to 0.1%	4
Output Propagation Delay	tPD		1		ns		4
Glitch Impulse			5		pV-s		4
Output Noise (IOUTFS = 20 mA)			50		pA/√Hz	IOUTFS = 20 mA	4
Input Setup Time	tS		2		ns		5
Input Hold Time	tH		1.5		ns		5
Thermal Resistance, 32-Lead LFCSP	θJA		32.5		°C/W	4-layer board in still air, per EIA/JESD51-7	6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	COPPER		1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER	7

CAD (KiCad official)

Symbol: AD9748ACPZ
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
3D model files: ad9748acpz-etched.step / ad9748acpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9748acpz.step / ad9748acpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (24 pp, sha256 81e2348c5aba062a, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD9748ACPZ

Verified AD9748ACPZ

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3D Model

Symbol & Footprint

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Datasheet

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