component
PL84051
Public Made by Adomby adom
POWLICON DC-DC Converters, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPL84051
POWLICON · DC-DC Converters · QFN-32-EP(5x5)
PL84051 from POWLICON, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BST | passive | Boost pin for the high-side MOSFET driver; the only stated limit is BST to SW at -0.3 V to 7 V. |
| 2 | VIN | power_in | Input voltage pin (datasheet text reads 'Iput Voltag.'); VIN is rated to 40 V absolute maximum with 4.5 V to 32 V operating range. |
| 3 | VIN | power_in | Input voltage pin (datasheet text reads 'Iput Voltag.'); VIN is rated to 40 V absolute maximum with 4.5 V to 32 V operating range. |
| 4 | DVIN | power_in | Power node of VIN for the power stage, rated to the 40 V absolute maximum. |
| 5 | PGND | power_in | Power ground; connect PGND and AGND together at the thermal pad under the IC. |
| 6 | EN | input | Logic high enables the converter (operation threshold 1.2 V typ., standby below 1.1 V); logic low disables everything except LDO2. |
| 7 | LDO1 | passive | Connect LDO1 to LDO2 (pin 13). |
| 8 | VDD | power_out | 5.4 V power supply for the PL84051 control core (5.4 V at VIN = 15 V). |
| 9 | VADJ | input | Accepts a 0-2 V analog voltage or PWM signal to program the VREF reference; tying it to VDD forces VREF to a constant 2 V. |
| 10 | IADJ | input | Accepts a 0-2 V analog voltage or PWM signal to program the IREF reference; tying it to VDD forces IREF to 2 V. |
| 11 | IREF | passive | Reference voltage for the input and output current-limiting loop, programmed via IADJ; a large capacitor (470 nF recommended) is advised for soft-start. |
| 12 | VREF | power_in | Voltage reference for the voltage control loop, 2 V in discharge mode and 1.8 V in charge mode when VADJ is tied to VDD. |
| 13 | LDO2 | power_out | Low quiescent current 5 V / 55 mA LDO powered directly from VIN, remaining active to power the MCU when EN is low. |
| 14 | AGND | power_in | Analog ground; connect to PGND together at the thermal pad under the IC. |
| 15 | FREQ | input | Sets switching frequency: connect to GND for 150 kHz, to VDD for 300 kHz, or to a VDD-GND resistor divider for 600 kHz or 1200 kHz. |
| 16 | COMP | passive | Error amplifier output (compensation node) of the control loop. |
| 17 | FB | input | VBUS voltage feedback input; a resistor divider from VBUS to GND programs the output, referenced to the internal 2 V VFB. |
| 18 | CSN | input | Minus input of the output current sense; average current limit is 40 mV / RSNS. |
| 19 | CSP | input | Positive input of the output current sense; shorting CSP to CSN disables the average current loop. |
| 20 | PGND | power_in | Power ground; connect PGND and AGND together at the thermal pad under the IC. |
| 21 | SW | output | Switching point of the power stage, rated to the 40 V absolute maximum for SW. |
| 22 | VBUS | power_in | Connect to the VBUS rail; VBUS UVLO rising threshold is 3.5 V with 300 mV hysteresis, and VBUS is rated to 40 V absolute maximum. |
| 23 | VCC | power_out | 6.6 V power supply for the high-side and low-side gate drivers (at VIN = 15 V). |
| 24 | PGND | power_in | Power ground; connect PGND and AGND together at the thermal pad under the IC. |
| 25 | PGND | power_in | Power ground; connect PGND and AGND together at the thermal pad under the IC. |
| 26 | PGND | power_in | Power ground; connect PGND and AGND together at the thermal pad under the IC. |
| 27 | PGND | power_in | Power ground; connect PGND and AGND together at the thermal pad under the IC. |
| 28 | SW | output | Switching point of the power stage, rated to the 40 V absolute maximum for SW. |
| 29 | DVIN | power_in | Power node of VIN for the power stage, rated to the 40 V absolute maximum. |
| 30 | DVIN | power_in | Power node of VIN for the power stage, rated to the 40 V absolute maximum. |
| 31 | DVIN | power_in | Power node of VIN for the power stage, rated to the 40 V absolute maximum. |
| 32 | DVIN | power_in | Power node of VIN for the power stage, rated to the 40 V absolute maximum. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | POWLICON |
| Package | QFN-32-EP(5x5) |
| Category | Power Supply Chip |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN input voltage | VIN | 4.5 | 32 | V | 5 | ||
| VBUS bus line voltage | VBUS | 2 | 30 | V | 5 | ||
| EN operation threshold | VEN_UV | 1.1 | 1.2 | 1.3 | V | 5 | |
| VIN, VDIN, VBUS, CSN, CSP, SW to GND | -0.3 | 40 | V | 4 | |||
| BST to SW | -0.3 | 7 | V | 4 | |||
| VCC to GND | VCC | -0.3 | 7 | V | 4 | ||
| CSP to CSN | -0.3 | 0.6 | V | 4 | |||
| VBUS to CSP, CSN | -0.3 | 0.6 | V | 4 | |||
| Other pins to GND | -0.3 | 6 | V | 4 | |||
| Storage temperature range | TST | -65 | 150 | °C | 4 | ||
| Input voltages VIN, VDIN, VBUS | 3.6 | 32 | V | 4 | |||
| Operating junction temperature range | TJ | -40 | 125 | °C | 4 | ||
| Junction to ambient thermal resistance | θJA | 44 | °C/W | QFN5X5-32 package; measured on approximately 1 in square of 1 oz copper (Note 3) | 4 | ||
| Junction to case thermal resistance | θJC | 9 | °C/W | QFN5X5-32 package (Note 3) | 4 |
CAD (KiCad official)
- Symbol:
PL84051 - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
pl84051-etched.step/pl84051-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pl84051.step/pl84051.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: POWLICON datasheet (13 pp, sha256
b30438aee8ea91a4, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).