component
CDCLVC1110PWR
Public Made by Adomby adom
Texas Instruments Clock Buffers, Drivers, Distributors, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownCDCLVC1110PWR
Texas Instruments · Clock Buffers, Drivers, Distributors · TSSOP-20
CDCLVC1110PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLKIN | input | LVCMOS clock input pin accepting DC to 250 MHz for VDD=3.3V or DC to 180 MHz for VDD=2.5V. |
| 2 | 1G | input | Asynchronous output enable control; when driven low, all outputs transition to low state within 6 ns. |
| 3 | Y0 | output | LVCMOS clock output; unused outputs can be left floating to reduce component cost. |
| 4 | GND | power_in | Device ground (return path for power supply). |
| 5 | VDD | power_out | Device power supply, 2.5V or 3.3V as configured. |
| 6 | Y4 | output | LVCMOS clock output with propagation delay of 2.0 ns (typ) at VDD=3.3V. |
| 7 | GND | power_in | Device ground (return path for power supply). |
| 8 | Y6 | output | LVCMOS clock output with output skew less than 50 ps between channels. |
| 9 | VDD | power_out | Device power supply, 2.5V or 3.3V as configured. |
| 10 | Y9 | output | LVCMOS clock output with rise/fall time of 0.8 ns at VDD=3.3V. |
| 11 | GND | power_in | Device ground (return path for power supply). |
| 12 | Y8 | output | LVCMOS clock output with maximum additive jitter of 100 fs for 3.3V operation. |
| 13 | Y7 | output | LVCMOS clock output with part-to-part skew of 0.5 ns at VDD=3.3V. |
| 14 | VDD | power_out | Device power supply, 2.5V or 3.3V as configured. |
| 15 | Y5 | output | LVCMOS clock output; output disable time to high-impedance is 6 ns maximum at VDD=3.3V. |
| 16 | GND | power_in | Device ground (return path for power supply). |
| 17 | Y2 | output | LVCMOS clock output with output enable time of 6 ns maximum at VDD=3.3V. |
| 18 | VDD | power_out | Device power supply, 2.5V or 3.3V as configured. |
| 19 | Y3 | output | LVCMOS clock output with typical output impedance of 45 Ω at VDD=3.3V. |
| 20 | Y1 | output | LVCMOS clock output with high-level output voltage (VOH) of 2.5V minimum at IOH=−8 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Clock/Timing |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
CDCLVC1110PWR - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
cdclvc1110pwr-etched.step/cdclvc1110pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cdclvc1110pwr.step/cdclvc1110pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (37 pp, sha256
7b5ccb44b8bc0016, retrieved 2026-09-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).