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CD74HC259M96

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Texas Instruments Latches, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd74hc259m96factory-2.0.0extractor-text

Verified CD74HC259M96

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CD74HC259M96 · SOIC-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 22-page datasheet
  • ✓distributor: lcsc C6539, digikey 296-CD74HC259M96TR-ND, mouser 595-CD74HC259M96
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-7_mfx_cu/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cd74hc259m96.kicad_sym✓ cd74hc259m96.kicad_mod✓ cd74hc259m96.step
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Contents

README

markdown

CD74HC259M96

Texas Instruments · Latches · SOIC-16

CD74HC259M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S0 input Address select input bit 0 (LSB) that chooses which of the eight latches is addressed.
2 S1 input Address select input bit 1 that chooses which of the eight latches is addressed.
3 S2 input Address select input bit 2 (MSB) that chooses which of the eight latches is addressed.
4 Q0 output Latch 0 output (S2 S1 S0 = LLL), active-high with buffered output drive.
5 Q1 output Latch 1 output (S2 S1 S0 = LLH), active-high with buffered output drive.
6 Q2 output Latch 2 output (S2 S1 S0 = LHL), active-high with buffered output drive.
7 Q3 output Latch 3 output (S2 S1 S0 = LHH), active-high with buffered output drive.
8 GND power_in Ground reference for the device.
9 Q4 output Latch 4 output (S2 S1 S0 = HLL), active-high with buffered output drive.
10 Q5 output Latch 5 output (S2 S1 S0 = HLH), active-high with buffered output drive.
11 Q6 output Latch 6 output (S2 S1 S0 = HHL), active-high with buffered output drive.
12 Q7 output Latch 7 output (S2 S1 S0 = HHH), active-high with buffered output drive.
13 D input Data input that is written into the addressed latch when G is low.
14 G input Enable input (overbar on pinout); with CLR high, G low writes data to the addressed latch and G high holds all latches (memory mode).
15 CLR input Clear input, active low; with G high, CLR low forces all outputs low, and with G low it selects 8-line demultiplexer mode.
16 VCC power_in Supply voltage, 2 V to 6 V for HC types (4.5 V to 5.5 V for HCT types), with a 0.1-uF bypass capacitor recommended.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range (HC types) VCC 2 6 V HC types 4
Input voltage VI 0 V maximum printed as VCC 4
Output voltage VO 0 V maximum printed as VCC 4
Input rise and fall time tt 1000 ns VCC = 2 V 4
Input rise and fall time tt 500 ns VCC = 4.5 V 4
Input rise and fall time tt 400 ns VCC = 6 V 4
Temperature range TA -55 125 °C 4
Supply voltage VCC -0.5 7 V 4
Input clamp diode current IIK -20 20 mA For VI < -0.5V or VI > VCC + 0.5V 4
Output clamp diode current IOK -20 20 mA For VO < -0.5V or VO > VCC + 0.5V 4
Drain current, per output IO -25 25 mA For -0.5V < VO < VCC + 0.5V 4
Output source or sink current per output pin IO -25 25 mA For VO > -0.5V or VO < VCC + 0.5V 4
Continuous current through VCC or GND -50 50 mA 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Lead temperature (soldering) 300 °C Soldering 10s (SOIC - lead tips only) 4
Junction-to-ambient thermal resistance RθJA 73 °C/W D (SOIC) package, 16 pins 4
High-level input voltage VIH 1.5 V VCC = 2 V 5
High-level input voltage VIH 3.15 V VCC = 4.5 V 5
High-level input voltage VIH 4.2 V VCC = 6 V 5
Low-level input voltage VIL 0.5 V VCC = 2 V 5
Low-level input voltage VIL 1.35 V VCC = 4.5 V 5
Low-level input voltage VIL 1.8 V VCC = 6 V 5
High-level output voltage VOH 1.9 V IOH = -20 µA, VCC = 2 V 5
High-level output voltage VOH 4.4 V IOH = -20 µA, VCC = 4.5 V 5
High-level output voltage VOH 5.9 V IOH = -20 µA, VCC = 6 V 5
High-level output voltage VOH 3.7 V IOH = -4 mA, VCC = 4.5 V, -55°C to 125°C 5
High-level output voltage VOH 5.2 V IOH = -5.2 mA, VCC = 6 V, -55°C to 125°C 5
Low-level output voltage VOL 0.1 V IOL = 20 µA, VCC = 2 V 5
Low-level output voltage VOL 0.4 V IOL = 4 mA, VCC = 4.5 V, -55°C to 125°C 5
Input leakage current II -1 0.1 1 µA VI = VCC or GND, VCC = 6 V, -55°C to 125°C; typ at 25°C 5
Supply current ICC 8 160 µA VI = VCC or GND, VCC = 6 V; typ at 25°C, max at -55°C to 125°C 5

CAD (KiCad official)

  • Symbol: CD74HC259M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc259m96-etched.step / cd74hc259m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc259m96.step / cd74hc259m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (22 pp, sha256 54cad389d9471eee, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF