component
LM5141RGET
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownLM5141RGET
Texas Instruments · DC-DC Converters · VQFN-24(4x4)
LM5141RGET from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DEMB | input | Diode emulation pin: connect to AGND to enable diode emulation, or to VDDA for forced PWM operation; it can also serve as a synchronization input to an external clock. |
| 2 | VDDA | power_out | Internal analog bias regulator output; connect a capacitor from VDDA to AGND. |
| 3 | AGND | power_in | Analog ground connection and return for the internal voltage reference and analog circuits. |
| 4 | RT | input | A resistor from RT to ground shifts the oscillator frequency from 2.2 MHz (1.8 MHz to 2.53 MHz) or from 440 kHz (300 kHz to 500 kHz); an analog voltage applied through a resistor can also shift it. |
| 5 | DITH | output | A capacitor from DITH to AGND is charged and discharged with a 20 µA source to dither the oscillator between -5% and +5%; connecting DITH to VDDA disables dithering. |
| 6 | OSC | input | Frequency select: connect to VDDA for 2.2 MHz oscillator frequency or to AGND for 440 kHz. |
| 7 | LOL | output | Low-side gate driver turn-off output; LO and LOL to PGND are rated -0.3 V to VCC + 0.3 V (absolute maximum). |
| 8 | LO | output | Low-side gate driver turn-on output; LO and LOL to PGND are rated -0.3 V to VCC + 0.3 V (absolute maximum). |
| 9 | PGND | power_in | Power ground connection for the low-side NMOS gate driver. |
| 10 | VCC | power_out | VCC bias supply pin; connect a capacitor from VCC to PGND. Recommended operating range is 5 V to 5.25 V for VCC and VDD combined with the -0.3 V lower limit. |
| 11 | HB | power_in | High-side driver supply for bootstrap gate drive; HB to SW is rated -0.3 V to 6.5 V absolute maximum and 5 V to 5.25 V recommended. |
| 12 | SW | passive | Switching node of the buck regulator; connect to the bootstrap capacitor, the high-side MOSFET source and the low-side MOSFET drain. SW to PGND is rated -0.3 V to 70 V absolute maximum. |
| 13 | HO | output | High-side gate driver turn-on output; HO and HOL to SW are rated -0.3 V to HB + 0.3 V. |
| 14 | HOL | output | High-side gate driver turn-off output; HO and HOL to SW are rated -0.3 V to HB + 0.3 V. |
| 15 | VIN | power_in | Supply voltage input for the VCC regulator; 3.8 V to 65 V recommended, with 70 V absolute maximum. |
| 16 | VCCX | power_in | Optional external bias input; if VCCX is above 4.5 V it connects internally to VCC and disables the internal VCC regulator, and it should be grounded if unused. |
| 17 | VOUT | input | Current sense amplifier input connected to the output side of the current sense resistor; VOUT and CS are rated 1.5 V to 15 V recommended. |
| 18 | CS | input | Current sense amplifier input; make a low-current Kelvin connection to the inductor side of the external current sense resistor, with 1.5 V to 15 V recommended. |
| 19 | FB | input | Connect to VDDA for a fixed 3.3 V output or to AGND for a fixed 5 V output; a divider sets 1.5 V to 15 V with a 1.2 V regulation threshold. |
| 20 | COMP | input | Output of the transconductance error amplifier, used for loop compensation. |
| 21 | PG | output | Open-collector power-good output that switches low when VOUT is outside the power-good window; rated -0.3 V to 6.5 V absolute maximum. |
| 22 | SS | input | Soft-start programming pin; an external capacitor and an internal 20 µA source set the ramp, and pulling SS below 80 mV turns off the gate driver outputs. |
| 23 | EN | input | Active-high logic input that enables the controller; EN to PGND is rated -0.3 V to 70 V absolute maximum. |
| 24 | RES | output | Restart timer pin; the external capacitor sets the hiccup off time after 512 consecutive PWM cycles of cycle-by-cycle current limiting, and connecting RES to VDD at power-up disables hiccup mode. |
| 25 | Thermal Pad | power_in | Exposed thermal pad on the package bottom; connect to AGND and PGND on the PCB. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage (absolute maximum) | VIN | -0.3 | 70 | V | 4 | ||
| SW to PGND | -0.3 | 70 | V | 4 | |||
| SW to PGND (20 ns transient) | -5 | V | 20 ns transient | 4 | |||
| HB to SW | -0.3 | 6.5 | V | 4 | |||
| HB to SW (20 ns transient) | -5 | V | 20 ns transient | 4 | |||
| HO, HOL to SW (max printed as HB + 0.3) | -0.3 | V | 4 | ||||
| HO, HOL to SW (20 ns transient) | -5 | V | 20 ns transient | 4 | |||
| LO, LOL to PGND (max printed as VCC + 0.3) | -0.3 | V | 4 | ||||
| LO, LOL to PGND (20 ns transient) | -1.5 | V | 20 ns transient | 4 | |||
| OSC, SS, COMP, RES, DEMB, RT, DITH (max printed as VDD + 0.3) | -0.3 | V | 4 | ||||
| EN to PGND | -0.3 | 70 | V | 4 | |||
| VCC, VCCX, VDD, PG, FB | -0.3 | 6.5 | V | 4 | |||
| VOUT, CS | -0.3 | 15.5 | V | 4 | |||
| PGND to AGND | -0.3 | 0.3 | V | 4 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Input voltage (recommended) | VIN | 3.8 | 65 | V | 5 | ||
| SW to PGND (recommended) | -0.3 | 65 | V | 5 | |||
| HB to SW (recommended) | -0.3 | 5 | 5.25 | V | 5 | ||
| HO, HOL to SW (recommended, max printed as HB + 0.3) | -0.3 | V | 5 | ||||
| LO, LOL to PGND (recommended) | -0.3 | 5 | 5.25 | V | 5 | ||
| FB, PG, OSC, SS, RES, DEMB, VCCX (recommended) | -0.3 | 5 | V | 5 | |||
| EN to PGND (recommended) | -0.3 | 65 | V | 5 | |||
| VCC, VDD (recommended) | -0.3 | 5 | 5.25 | V | 5 | ||
| VOUT, CS (recommended) | 1.5 | 5 | 15 | V | 5 | ||
| PGND to AGND (recommended) | -0.3 | 0.3 | V | 5 | |||
| Operating junction temperature (recommended) | TJ | -40 | 125 | °C | 5 | ||
| Shutdown mode current | ISHUTDOWN | 10 | 12.5 | µA | VIN = 8–18 V, EN = 0 V, VCCX = 0 V | 6 | |
| Standby current | ISTANDBY | 35 | 45 | µA | EN = 5 V, FB = VDD, VOUT in regulation, no-load, not switching, DEMB = GND. | 6 | |
| VCC regulation voltage | VCC(REG) | 4.75 | 5 | 5.25 | V | VIN = 6–18 V, 0–75 mA, VCCX = 0 V | 6 |
| VCC under voltage threshold | VCC(UVLO) | 3.25 | 3.4 | 3.55 | V | VCC rising, VCCX = 0 V | 6 |
| VCC sourcing current limit | ICC(LIM) | 85 | 125 | mA | VCCX = 0 V | 6 | |
| Internal bias supply power (VDDA regulation) | VDDA(REG) | 4.75 | 5 | 5.25 | V | VCCX = 0 V | 6 |
| VDDA under voltage threshold | VDDA(UVLO) | 3.1 | 3.2 | 3.3 | V | VCC rising, VCCX = 0 V | 6 |
| VCCX on threshold | VCCX(ON) | 4.1 | 4.3 | 4.4 | V | VCC rising | 6 |
| Current limit threshold | V(CS) | 68 | 75 | 82 | mV | ILSET = VDDA, measure from CS to VOUT | 6 |
| Current sense amplifier gain | 11.4 | 12 | 12.6 | V/V | 6 | ||
| Output voltage regulation, 3.3 V option | 3.273 | 3.3 | 3.327 | V | VIN = 3.8–42 V | 6 | |
| Output voltage regulation, 5 V option | 4.96 | 5 | 5.04 | V | VIN = 5.5–42 V | 6 | |
| Regulated feedback voltage | 1.193 | 1.2 | 1.207 | V | 6 | ||
| Transconductance amplifier gain, feedback to COMP | Gm | 1010 | 1200 | µS | 7 | ||
| PG under voltage trip level | PG(UV) | 90 | 92 | 94 | % | Falling with respect to the regulation voltage | 7 |
| PG over voltage trip level | PG(OVP) | 108 | 110 | 112 | % | Rising with respect to the regulation voltage | 7 |
| DEMB input low frequency range | 350 | 550 | kHz | 440 kHz | 8 | ||
| DEMB input high frequency range | 1800 | 2600 | kHz | 2.2 MHz | 8 | ||
| Soft-start current | ISS | 16 | 22 | 28 | µA | 8 | |
| HO off to LO on dead time | tdly1 | 20 | 40 | ns | 7 | ||
| LO off to HO on dead time | tdly2 | 20 | 38 | ns | 7 | ||
| Oscillator frequency 2.2 MHz | 2100 | 2200 | 2300 | kHz | OSC = VDDA, VIN = 8–18 V | 8 | |
| Oscillator frequency 440 kHz | 420 | 440 | 460 | kHz | OSC = GND, VIN = 8–18 V | 8 | |
| RT adjustment range, 2.2 MHz minimum | 1710 | 1800 | 1890 | kHz | OSC = VDD, RTMIN = 61.9 kΩ | 8 | |
| RT adjustment range, 2.2 MHz typical | 2100 | 2200 | 2300 | kHz | OSC = VDD, RTTYP = 49.9 kΩ | 8 | |
| RT adjustment range, 2.2 MHz maximum | 2405 | 2530 | 2655 | kHz | OSC = VDD, RTMAX = 43.2 kΩ | 8 | |
| RT adjustment range, 440 kHz minimum | 285 | 300 | 315 | kHz | OSC = GND, RTMIN = 73.2 kΩ | 8 | |
| RT adjustment range, 440 kHz typical | 420 | 440 | 460 | kHz | OSC = GND, RTTYP = 49.9 kΩ | 8 | |
| RT adjustment range, 440 kHz maximum | 475 | 500 | 525 | kHz | OSC = GND, RTMAX = 44.2 kΩ | 8 | |
| Minimum on-time | ton | 45 | 66 | ns | 8 | ||
| Junction-to-ambient thermal resistance | RθJA | 34.1 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 12.1 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 2.9 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
LM5141RGET - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
lm5141rget-etched.step/lm5141rget-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5141rget.step/lm5141rget.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (53 pp, sha256
7e612d227f860930, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).