component
24LC65
Public Made by Adomby adom
Microchip Tech Pre-ordered MCUs, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown24LC65
Microchip Tech · Pre-ordered MCUs · PDIP-8
24LC65 from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | User-configurable chip address input whose level, together with A1 and A2, defines the address block the device occupies and must match the bits sent in the control byte. |
| 2 | A1 | input | User-configurable chip address input whose level, together with A0 and A2, defines the address block the device occupies and must match the bits sent in the control byte. |
| 3 | A2 | input | User-configurable chip address input whose level, together with A0 and A1, defines the address block the device occupies and must match the bits sent in the control byte. |
| 4 | VSS | power_in | Ground reference for the device. |
| 5 | SDA | bidirectional | Open-drain serial address/data I/O that requires a pull-up resistor to VCC (typically 10 kΩ for 100 kHz, 2 kΩ for 400 kHz) and may change only while SCL is low, except for Start and Stop conditions. |
| 6 | SCL | input | Serial clock input used to synchronize data transfer to and from the device. |
| 7 | NC | unconnected | No internal connection. |
| 8 | VCC | power_in | Power supply, +1.8V to 6.0V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | PDIP-8 |
| Category | Embedded Processors & Controllers |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-level input voltage | VIH | 0.7 | VCC | 3 | |||
| Low-level input voltage | VIL | 0.3 | VCC | 3 | |||
| Hysteresis of Schmitt Trigger inputs | VHYS | 0.05 | VCC | 3 | |||
| Low-level output voltage | VOL | 0.4 | V | IOL = 3.0 mA | 3 | ||
| Input leakage current | ILI | -1 | 1 | μA | VIN = .1V to VCC | 3 | |
| Output leakage current | ILO | -1 | 1 | μA | VOUT = .1V to VCC | 3 | |
| Pin capacitance (all inputs/outputs) | CIN, COUT | 10 | pF | VCC = 5.0V; TA = 25°C, FCLK = 1 MHz | 3 | ||
| Operating current, write | ICC Write | 3 | mA | VCC = 6.0V, SCL = 400 kHz | 3 | ||
| Operating current, read | ICC Read | 150 | μA | VCC = 6.0V, SCL = 400 kHz | 3 | ||
| Standby current | ICCS | 5 | μA | VCC = 5.0V, SCL = SDA = VCC, A0, A1, A2 = VSS | 3 | ||
| Clock frequency | FCLK | 100 | kHz | VCC = 1.8V-6.0V, STD. Mode | 4 | ||
| Clock frequency | FCLK | 400 | kHz | VCC = 4.5-6.0V, FAST Mode | 4 | ||
| Clock high time | THIGH | 4000 | ns | VCC = 1.8V-6.0V, STD. Mode | 4 | ||
| Clock high time | THIGH | 600 | ns | VCC = 4.5-6.0V, FAST Mode | 4 | ||
| Clock low time | TLOW | 4700 | ns | VCC = 1.8V-6.0V, STD. Mode | 4 | ||
| Clock low time | TLOW | 1300 | ns | VCC = 4.5-6.0V, FAST Mode | 4 | ||
| SDA and SCL rise time | TR | 1000 | ns | VCC = 1.8V-6.0V, STD. Mode | 4 | ||
| SDA and SCL rise time | TR | 300 | ns | VCC = 4.5-6.0V, FAST Mode | 4 | ||
| SDA and SCL fall time | TF | 300 | ns | VCC = 1.8V-6.0V, STD. Mode | 4 | ||
| Start condition setup time (start hold) | THD:STA | 4000 | ns | VCC = 1.8V-6.0V, STD. Mode; after this period the first clock pulse is generated | 4 | ||
| Start condition setup time (start hold) | THD:STA | 600 | ns | VCC = 4.5-6.0V, FAST Mode; after this period the first clock pulse is generated | 4 | ||
| Start condition setup time (repeated start) | TSU:STA | 4700 | ns | VCC = 1.8V-6.0V, STD. Mode; only relevant for repeated Start condition | 4 | ||
| Start condition setup time (repeated start) | TSU:STA | 600 | ns | VCC = 4.5-6.0V, FAST Mode; only relevant for repeated Start condition | 4 | ||
| Data input hold time | THD:DAT | 0 | ns | VCC = 1.8V-6.0V, STD. Mode | 4 | ||
| Data input setup time | TSU:DAT | 250 | ns | VCC = 1.8V-6.0V, STD. Mode | 4 | ||
| Data input setup time | TSU:DAT | 100 | ns | VCC = 4.5-6.0V, FAST Mode | 4 | ||
| Stop condition setup time | TSU:STO | 4000 | ns | VCC = 1.8V-6.0V, STD. Mode | 4 | ||
| Stop condition setup time | TSU:STO | 600 | ns | VCC = 4.5-6.0V, FAST Mode | 4 | ||
| Output valid from clock | TAA | 3500 | ns | VCC = 1.8V-6.0V, STD. Mode | 4 | ||
| Output valid from clock | TAA | 900 | ns | VCC = 4.5-6.0V, FAST Mode | 4 | ||
| Bus free time | TBUF | 4700 | ns | VCC = 1.8V-6.0V, STD. Mode; time the bus must be free before a new transmission can start | 4 | ||
| Bus free time | TBUF | 1300 | ns | VCC = 4.5-6.0V, FAST Mode; time the bus must be free before a new transmission can start | 4 | ||
| Output fall time from VIH min to VIL max | TOF | 250 | ns | VCC = 1.8V-6.0V, STD. Mode; CB ≤ 100 pF | 4 | ||
| Input filter spike suppression (SDA and SCL pins) | TSP | 50 | ns | VCC = 1.8V-6.0V, STD. Mode | 4 | ||
| Write cycle time | TWR | 5 | ms/page | VCC = 1.8V-6.0V, STD. Mode; single page of 8 bytes | 4 | ||
| Endurance, High Endurance Block | 10 | M cycles | 25°C | 4 | |||
| Endurance, Rest of Array | 1 | M cycles | 25°C | 4 | |||
| Supply voltage VCC (24LC65) | VCC | 2.5 | 6 | V | 24LC65 VCC range per device selection table | 1 | |
| Commercial (C) ambient temperature | TA | 0 | 70 | °C | Commercial (C) | 3 | |
| Industrial (I) ambient temperature | TA | -40 | 85 | °C | Industrial (I) | 3 | |
| All inputs and outputs w.r.t. VSS | -0.6 | V | Printed maximum is VCC +1.0V (formula, not converted) | 3 | |||
| Storage temperature | -65 | 150 | °C | 3 | |||
| Ambient temperature with power applied | -40 | 125 | °C | 3 | |||
| ESD protection on all pins | 4 | kV | 3 |
CAD (KiCad official)
- Symbol:
24LC65 - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: PDIP-8 (KiCad packages3D, STEP)
- 3D model files:
24lc65-etched.step/24lc65-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);24lc65.step/24lc65.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (24 pp, sha256
24ef25e48afcd58d, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).