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74LVT08PW

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Nexperia Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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74LVT08PW

Nexperia · Logic Gates · TSSOP-14

74LVT08PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input 1A of AND gate 1; overvoltage tolerant, with recommended input voltage range 0 V to 5.5 V.
2 1B input Data input 1B of AND gate 1; recommended input voltage range 0 V to 5.5 V.
3 1Y output Data output 1Y of AND gate 1; output current limits are +64 mA in the LOW-state and -32 mA in the HIGH-state.
4 2A input Data input 2A of AND gate 2; recommended input voltage range 0 V to 5.5 V.
5 2B input Data input 2B of AND gate 2; recommended input voltage range 0 V to 5.5 V.
6 2Y output Data output 2Y of AND gate 2; output current limits are +64 mA in the LOW-state and -32 mA in the HIGH-state.
7 GND power_in Ground (0 V); all voltage ratings are referenced to this pin.
8 3Y output Data output 3Y of AND gate 3; output current limits are +64 mA in the LOW-state and -32 mA in the HIGH-state.
9 3A input Data input 3A of AND gate 3; recommended input voltage range 0 V to 5.5 V.
10 3B input Data input 3B of AND gate 3; recommended input voltage range 0 V to 5.5 V.
11 4Y output Data output 4Y of AND gate 4; output current limits are +64 mA in the LOW-state and -32 mA in the HIGH-state.
12 4A input Data input 4A of AND gate 4; recommended input voltage range 0 V to 5.5 V.
13 4B input Data input 4B of AND gate 4; recommended input voltage range 0 V to 5.5 V.
14 VCC power_in Supply voltage; recommended range 2.7 V to 3.6 V, absolute maximum -0.5 V to +4.6 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 4.6 V 3
input voltage VI -0.5 7 V 3
output voltage VO -0.5 7 V output in OFF-state or HIGH-state 3
input clamping current IIK -50 mA VI < 0 V 3
output clamping current IOK -50 mA VO < 0 V 3
output current IO 64 mA output in LOW-state 3
output current IO -32 mA output in HIGH-state 3
storage temperature Tstg -65 150 °C 3
junction temperature Tj 150 °C 3
total power dissipation Ptot 500 mW Tamb = -40 to +85 °C 3
supply voltage VCC 2.7 3.6 V 3
input voltage VI 0 5.5 V 3
HIGH-level output current IOH -20 mA 3
LOW-level output current IOL 32 mA 3
ambient temperature Tamb -40 85 °C in free-air 3
input transition rise and fall rate Δt/ΔV 10 ns/V outputs enabled 3
input clamping voltage VIK -1.2 V VCC = 2.7 V; IIK = -18 mA 4
HIGH-level input voltage VIH 2 V 4
LOW-level input voltage VIL 0.8 V 4
HIGH-level output voltage VOH 2.4 V VCC = 2.7 V; IOH = -6 mA 4
HIGH-level output voltage VOH 2 V VCC = 3.0 V; IOH = -20 mA 4
LOW-level output voltage VOL 0.2 V VCC = 2.7 V; IOL = 100 μA 4
LOW-level output voltage VOL 0.5 V VCC = 2.7 V; IOL = 24 mA 4
input leakage current II 10 μA VCC = 0 V or 3.6 V; VI = 5.5 V 4
input leakage current II -1 1 μA VCC = 3.6 V; VI = VCC or GND 4
power-off leakage current IOFF -100 100 μA VCC = 0 V; VI or VO = 0 V to 4.5 V 4
supply current ICC 1 2 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A; output LOW 4
supply current ICC 0.02 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A; output HIGH 4
additional supply current per input pin ΔICC 0.2 mA VCC = 3.0 V to 3.6 V; one input at VCC - 0.6 V and other inputs at VCC or GND 4
propagation delay LOW to HIGH tPLH 4.7 ns VCC = 2.7 V; nA or nB to nY; see Fig. 4 4
propagation delay LOW to HIGH tPLH 1 3 3.9 ns VCC = 3.0 V to 3.6 V; nA or nB to nY; see Fig. 4 4
propagation delay HIGH to LOW tPHL 4.8 ns VCC = 2.7 V; nA or nB to nY; see Fig. 4 4
propagation delay HIGH to LOW tPHL 1 3.4 4.6 ns VCC = 3.0 V to 3.6 V; nA or nB to nY; see Fig. 4 4
input capacitance CI 4 pF VI = 0 V or 3.0 V 4
output capacitance CO 10 pF VO = 0 V or 3.0 V 4

CAD (KiCad official)

  • Symbol: 74LVT08PW
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74lvt08pw-etched.step / 74lvt08pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvt08pw.step / 74lvt08pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (10 pp, sha256 fa487b4e2b33fbea, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF