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A89301GESSR

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Allegro MicroSystems, LLC Motor Driver ICs, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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A89301GESSR

Allegro MicroSystems, LLC · Motor Driver ICs · QFN-24-EP(4x4)

A89301GESSR from Allegro MicroSystems, LLC, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SENP input Current sense positive terminal for the bus shunt resistor; differential voltage to SENN should be less than 65 mV to avoid saturation (abs max ±500 mV DC).
2 GND power_in Ground.
3 GLA output Low-side gate drive output for phase A; source/sink current configurable in EEPROM (abs max VLSS-0.3 to 8.5 V).
4 GLB output Low-side gate drive output for phase B; source/sink current configurable in EEPROM (abs max VLSS-0.3 to 8.5 V).
5 GLC output Low-side gate drive output for phase C; source/sink current configurable in EEPROM (abs max VLSS-0.3 to 8.5 V).
6 LSS passive Low-side source connection for the low-side MOSFETs (abs max ±500 mV DC).
7 SA bidirectional Motor phase A output/high-side source sense (abs max -2 to VBB+2 V).
8 GHA output High-side gate drive output for phase A (abs max VSx-0.3 to VCP+0.3 V).
9 SB bidirectional Motor phase B output/high-side source sense (abs max -2 to VBB+2 V).
10 GHB output High-side gate drive output for phase B (abs max VSx-0.3 to VCP+0.3 V).
11 SC bidirectional Motor phase C output/high-side source sense (abs max -2 to VBB+2 V).
12 GHC output High-side gate drive output for phase C (abs max VSx-0.3 to VCP+0.3 V).
13 NC unconnected No connect.
14 VCP passive Charge pump output for high-side gate drive (abs max VBB-0.3 to VBB+8 V).
15 VBB power_in Power supply input, 5.5 to 50 V operating (48 V max while driving).
16 CP2 passive Charge pump capacitor terminal 2 (abs max VBB-0.3 to VCP+0.3 V).
17 CP1 passive Charge pump capacitor terminal 1 (abs max -0.3 to VBB+0.3 V).
18 BRAKE input Active-high logic input that turns on all low sides for braking and overrides speed control (logic range -0.3 to 6 V).
19 VREG power_out 2.8 V regulator output powering internal logic, usable for up to 10 mA external load, requires 0.22 µF or greater ceramic capacitor.
20 SPD input Speed demand input for PWM, analog or clock mode, also used as SCL in I2C mode (-0.3 to 6 V).
21 DIR input Direction control logic input: high gives A→B→C, low gives A→C→B (-0.3 to 6 V).
22 FAULT output Open-drain fault indicator output, high when no fault, recommended maximum sink current 10 mA (6 V max).
23 FG bidirectional Open-drain motor speed output pulled up to VREG or external 3.3/5 V, also used as SDA in I2C mode (6 V max).
24 SENN input Current sense negative terminal for the bus shunt resistor (abs max ±500 mV DC).
25 PAD passive Exposed pad for enhanced thermal dissipation.

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package QFN-24-EP(4x4)
Category Power Management ICs
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (Driving) VBB 5.5 48 V Driving 4
Supply Voltage (Operating) VBB 5.5 50 V Operating 4
VBB Supply Current IBB 8 12 mA IVREG = 0 mA 4
VBB Supply Current Standby IBB 10 20 µA Standby mode 4
Reference Voltage VREG 2.7 2.86 2.95 V IOUT = 10 mA 4
High Side Gate Drive Output VGH 6.5 6.8 V VBB = 8 V 4
Low Side Gate Drive Output VGL 6.5 7.3 V VBB = 8 V 4
PWM Duty On Threshold PWMON -0.5 0.5 % Relative to target 4
PWM Duty Off Threshold PWMOFF -0.5 0.5 % Relative to target 4
PWM Input Frequency Range fPWM(MIN) 2.5 100 kHz PWM input frequency setting = 0 4
PWM Input Frequency Range fPWM(MIN) 80 3200 Hz PWM input frequency setting = 1 4
Clock Input Frequency Range fCLOCK 1 2000 Hz CLOCK mode 4
SPD Standby Threshold (Analog Enter) VSPD(TH_ENT) 50 100 150 mV 4
SPD Standby Threshold (Analog Exit) VSPD(TH_EXIT) 0.4 0.75 1 V 4
SPD On Threshold VSPD(ON) 210 250 290 mV ON/OFF setting = 10% 4
SPD ADC Accuracy VSPDADC(ACC) -40 40 mV VSPD = 0.2 to 2.5 V 4
Speed Closed Loop Accuracy fSPD(ACC) -5 5 % PWM mode or Analog mode 4
Speed Closed Loop Accuracy fSPD(ACC) -0.1 0.1 rpm Clock mode 4
Motor PWM Frequency fPWM 23.3 24.4 25.3 kHz TA = 25°C 4
VBB UVLO VBB(UVLO) 4.75 4.95 V VBB rising 5
VBB UVLO Hysteresis VBB(HYS) 200 300 450 mV 5
Input Current IIN -5 1 5 µA SPD, FG; VIN = 0 to 5.5 V 5
Logic Input, Low Level VIL 0 0.8 V 5
Logic Input, High Level VIH 2 5.5 V 5
Logic Input Hysteresis VHYS 200 300 600 mV 5
FG Output Leakage IFG 1 µA V = 5.5 V 5
Supply Voltage VBB 50 V 2
Logic Input Voltage Range VIN -0.3 6 V SPD, BRAKE, DIR 2
Logic Output VO 6 V FG, FAULT (I < 5 mA) 2
LSS Voltage VLSS -500 500 mV DC 2
LSS Voltage VLSS -4 4 V tW < 500 ns 2
VREG Voltage VREG 0 4 V 2
SENN, SENP Voltage VSENN, VSENP -500 500 mV DC 2
SENN, SENP Voltage VSENN, VSENP -4 4 V tW < 500 ns 2
Output Voltage SA, SB, SC VOUT -2 V SA, SB, SC; upper limit printed as VBB+2 2
Output Voltage SA, SB, SC VOUT -4 V tw < 50 ns; upper limit printed as VBB+4 2
Junction Temperature TJ 150 °C 2
Storage Temperature Range Tstg -55 150 °C 2
Operating Temperature Range TA -40 105 °C Range G 2
Package Thermal Resistance RθJA 45 °C/W 24-contact QFN (package ES), on 2-sided PCB 1-in.2 copper 2
Thermal Shutdown Temperature TJTSD 165 °C Temperature increasing 5
Thermal Shutdown Hysteresis ΔTJ 20 °C Recovery = TJTSD, ΔTJ 5
Dead Time tDT 400 ns Code = 9 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin with exposed thermal pad (suffix ES). The package is lead (Pb) free, with 100% matte-tin leadframe plating. 1

CAD (KiCad official)

  • Symbol: A89301GESSR
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: a89301gessr-etched.step / a89301gessr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a89301gessr.step / a89301gessr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (20 pp, sha256 3621b7ecdce53c1a, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF