AT45DB021E-SSHN2B-T from Adesto Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SI	input	Serial Input: shifts in all command, address and data bits, latched on the rising edge of SCK and ignored when the device is deselected (CS high).
2	SCK	input	Serial Clock: controls data flow to and from the device, with input latched on the rising edge and output on SO clocked out on the falling edge of SCK.
3	RESET	input	Active-low reset: a low level terminates the operation in progress and holds the internal state machine idle; drive high externally if unused.
4	CS	input	Active-low Chip Select: asserting selects the device, deasserting deselects it into standby and puts SO in high impedance; a high-to-low transition starts an operation and low-to-high ends it.
5	WP	input	Active-low Write Protect: when asserted, sectors specified in the Sector Protection Register are protected from program and erase; internally pulled high, may be left floating if unused but should preferably be tied to VCC.
6	VCC	power_in	Device power supply (1.65V to 3.6V); operation at invalid VCC voltages may produce spurious results.
7	GND	power_in	Ground reference for the power supply, to be connected to system ground.
8	SO	output	Serial Output: shifts data out on the falling edge of SCK and is high-impedance whenever the device is deselected (CS high).

Key specifications

Parameter	Value
Manufacturer	Adesto Technologies
Package	SOIC-8
Category	Memory
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Temperature under Bias		-55		125	°C		44
Storage Temperature		-65		150	°C		44
All Input Voltages (except VCC, including NC pins) with respect to Ground		-0.6		6.25	V		44
All Output Voltages with respect to Ground (max = VCC + 0.6V)		-0.6		0.6	V	Maximum printed as VCC + 0.6V; value shown is the offset above VCC	44
Operating Temperature (Case), Industrial		-40		85	°C	Industrial grade	44
VCC Power Supply	VCC	1.65		3.6	V		44
Ultra-Deep Power-Down Current	IUDPD		0.2	1	µA	CS=VCC; all other inputs at 0V or VCC	45
Deep Power-Down Current	IDPD		4.5	12	µA	CS=VCC; all other inputs at 0V or VCC	45
Standby Current	ISB		25	40	µA	CS=VCC; all other inputs at 0V or VCC	45
Active Current, Low Power Read (01h) Operation	ICC1		6	9	mA	f = 1MHz; IOUT = 0mA	45
Active Current, Low Power Read (01h) Operation	ICC1		7	10	mA	f = 15MHz; IOUT = 0mA	45
Active Current, Read Operation	ICC2		10	12	mA	f = 50MHz; IOUT = 0mA	45
Active Current, Read Operation	ICC2		12	15	mA	f = 85MHz; IOUT = 0mA	45
Active Current, Program Operation	ICC3		10	12	mA	CS = VCC	45
Active Current, Erase Operation	ICC4		8	12	mA	CS = VCC	45
Input Load Current	ILI			1	µA	All inputs at CMOS levels	45
Output Leakage Current	ILO			1	µA	All inputs at CMOS levels	45
Input Low Voltage	VIL			0.2	x VCC	1.65V to 3.6V column; printed as VCC x 0.2	45
Input High Voltage	VIH	0.8			x VCC	1.65V to 3.6V column; printed as VCC x 0.8	45
Output Low Voltage	VOL			0.2	V	IOL = 100µA	45
Output High Voltage	VOH	0.2			V	IOH = -100µA; printed as VCC - 0.2V; value shown is the offset below VCC	45
SCK Frequency for Continuous Read (Low Power Mode, 01h Opcode)	fCAR3			15	MHz	Low Power Mode, 01h Opcode	46
SCK High Time	tWH	4			ns		46
SCK Low Time	tWL	4			ns		46
SCK Rise Time, Peak-to-peak	tSCKR			0.1	V/ns	Note 1: values based on device characterization, not 100% tested	46
SCK Fall Time, Peak-to-peak	tSCKF			0.1	V/ns	Note 1: values based on device characterization, not 100% tested	46
Minimum CS High Time	tCS	20			ns		46
CS Setup Time	tCSS	6			ns	1.65V to 3.6V column	46
CS Hold Time	tCSH	5			ns	1.65V to 3.6V column	46
Data In Setup Time	tSU	2			ns		46
Data In Hold Time	tH	1			ns		46
Output Hold Time	tHO	0			ns		46
Output Disable Time	tDIS			8	ns	Note 1: values based on device characterization, not 100% tested	46
Output Valid	tV			7	ns		46
WP Low to Protection Enabled	tWPE			1	µs		46
WP High to Protection Disabled	tWPD			1	µs		46
Freeze Sector Lockdown Time (from CS High)	tLOCK			200	µs	from CS High	46
CS High to Ultra-Deep Power-Down	tEUDPD			3	µs	Note 1: values based on device characterization, not 100% tested	46
Minimum CS Low Time to Exit Ultra-Deep Power-Down	tCSLU	20			ns		46
Exit Ultra-Deep Power-Down Time	tXUDPD			240	µs	1.65V to 3.6V column as printed (see review_required)	46
CS High to Deep Power-Down	tEDPD			2	µs	Note 1: values based on device characterization, not 100% tested	46
Resume from Deep Power-Down Time	tRDPD			35	µs		46
Page to Buffer Transfer Time	tXFR			100	µs		46
Page to Buffer Compare Time	tCOMP			100	µs		46
RESET Pulse Width	tRST	10			µs		46
RESET Recovery Time	tREC	1			µs		46
Software Reset Time	tSWRST			35	µs		46
Page Erase and Programming Time (256/264 bytes)	tEP		10	35	ms	1.65V to 3.6V column	47
Page Programming Time	tP		1.5	3	ms	1.65V to 3.6V column	47
Page Erase Time	tPE		6	25	ms		47
Block Erase Time	tBE		25	35	ms		47
Sector Erase Time	tSE		350	550	ms		47
Chip Erase Time	tCE		3	4	s		47
OTP Security Register Program Time	tOTPP		200	500	µs		47
Byte Programming Time	tBP		8		µs		47

CAD (KiCad official)

Symbol: AT45DB021E-SSHN2B-T
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: at45db021e-sshn2b-t-etched.step / at45db021e-sshn2b-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at45db021e-sshn2b-t.step / at45db021e-sshn2b-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Adesto Technologies datasheet (68 pp, sha256 db6fabc37825965c, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AT45DB021E-SSHN2B-T

Verified AT45DB021E-SSHN2B-T

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3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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