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STM8S207RBT6C

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STMicroelectronics ST Microelectronics, LQFP-64(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

README

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STM8S207RBT6C

STMicroelectronics · ST Microelectronics · LQFP-64(14x14)

STM8S207RBT6C from STMicroelectronics, in a LQFP-64(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NRST bidirectional Reset input/output pin (reset function after reset).
2 PA1/OSCIN bidirectional Port A1 with floating/wpu input, external interrupt, O1 slow output (up to 2 MHz); resonator/crystal input.
3 PA2/OSCOUT bidirectional Port A2 with floating/wpu input, external interrupt, O1 slow output (up to 2 MHz); resonator/crystal output.
4 VSSIO_1 power_in I/O ground.
5 VSS power_in Digital ground.
6 VCAP passive 1.8 V regulator capacitor pin.
7 VDD power_in Digital power supply.
8 VDDIO_1 power_in I/O power supply.
9 PA3/TIM2_CH3 bidirectional Port A3 with external interrupt, O1 output; Timer 2 channel 3 (remap to TIM3_CH1 via AFR1).
10 PA4/UART1_RX bidirectional Port A4 high sink, O3 output, external interrupt; UART1 receive (pulled up by ROM bootloader during activation).
11 PA5/UART1_TX bidirectional Port A5 high sink, O3 output, external interrupt; UART1 transmit.
12 PA6/UART1_CK bidirectional Port A6 high sink, O3 output, external interrupt; UART1 synchronous clock.
13 PF7/AIN15 bidirectional Port F7, O1 output; ADC analog input 15.
14 PF6/AIN14 bidirectional Port F6, O1 output; ADC analog input 14.
15 PF5/AIN13 bidirectional Port F5, O1 output; ADC analog input 13.
16 PF4/AIN12 bidirectional Port F4, O1 output; ADC analog input 12.
17 PF3/AIN11 bidirectional Port F3, O1 output; ADC analog input 11.
18 VREF+ power_in ADC positive reference voltage.
19 VDDA power_in Analog power supply.
20 VSSA power_in Analog ground.
21 VREF- power_in ADC negative reference voltage.
22 PF0/AIN10 bidirectional Port F0, O1 output; ADC analog input 10.
23 PB7/AIN7 bidirectional Port B7 with external interrupt, O1 output; ADC analog input 7.
24 PB6/AIN6 bidirectional Port B6 with external interrupt, O1 output; ADC analog input 6.
25 PB5/AIN5 bidirectional Port B5 with external interrupt, O1 output; ADC analog input 5 (I2C_SDA via AFR6 remap).
26 PB4/AIN4 bidirectional Port B4 with external interrupt, O1 output; ADC analog input 4 (I2C_SCL via AFR6 remap).
27 PB3/AIN3 bidirectional Port B3 with external interrupt, O1 output; ADC analog input 3 (TIM1_ETR via AFR5 remap).
28 PB2/AIN2 bidirectional Port B2 with external interrupt, O1 output; ADC analog input 2 (TIM1_CH3N via AFR5 remap).
29 PB1/AIN1 bidirectional Port B1 with external interrupt, O1 output; ADC analog input 1 (TIM1_CH2N via AFR5 remap).
30 PB0/AIN0 bidirectional Port B0 with external interrupt, O1 output; ADC analog input 0 (TIM1_CH1N via AFR5 remap).
31 PE7/AIN8 bidirectional Port E7 with external interrupt, O1 output; ADC analog input 8.
32 PE6/AIN9 bidirectional Port E6 with external interrupt, O1 output; ADC analog input 9.
33 PE5/SPI_NSS bidirectional Port E5 with external interrupt, O1 output; SPI master/slave select.
34 PC1/TIM1_CH1 bidirectional Port C1 high sink, O3 output, external interrupt; Timer 1 channel 1.
35 PC2/TIM1_CH2 bidirectional Port C2 high sink, O3 output, external interrupt; Timer 1 channel 2.
36 PC3/TIM1_CH3 bidirectional Port C3 high sink, O3 output, external interrupt; Timer 1 channel 3.
37 PC4/TIM1_CH4 bidirectional Port C4 high sink, O3 output, external interrupt; Timer 1 channel 4.
38 PC5/SPI_SCK bidirectional Port C5 high sink, O3 output, external interrupt; SPI clock.
39 VSSIO_2 power_in I/O ground.
40 VDDIO_2 power_in I/O power supply.
41 PC6/SPI_MOSI bidirectional Port C6 high sink, O3 output, external interrupt; SPI master out/slave in.
42 PC7/SPI_MISO bidirectional Port C7 high sink, O3 output, external interrupt; SPI master in/slave out.
43 PG0/CAN_TX bidirectional Port G0, O1 output; beCAN transmit, available on STM8S208xx devices only.
44 PG1/CAN_RX bidirectional Port G1, O1 output; beCAN receive, available on STM8S208xx devices only.
45 PG2 bidirectional Port G2, O1 output.
46 PG3 bidirectional Port G3, O1 output.
47 PG4 bidirectional Port G4, O1 output.
48 PI0 bidirectional Port I0, O1 output.
49 PG5 bidirectional Port G5, O1 output.
50 PG6 bidirectional Port G6, O1 output.
51 PG7 bidirectional Port G7, O1 output.
52 PE4 bidirectional Port E4 with external interrupt, O1 output.
53 PE3/TIM1_BKIN bidirectional Port E3 with external interrupt, O1 output; Timer 1 break input.
54 PE2/I2C_SDA bidirectional Port E2 true open drain (no weak pull-up) , O1; I2C data.
55 PE1/I2C_SCL bidirectional Port E1 true open drain (no weak pull-up), O1; I2C clock.
56 PE0/CLK_CCO bidirectional Port E0 high sink, O3 output, external interrupt; configurable clock output.
57 PD0/TIM3_CH2 bidirectional Port D0 high sink, O3 output, external interrupt; Timer 3 channel 2 (TIM1_BKIN via AFR3, CLK_CCO via AFR2).
58 PD1/SWIM bidirectional Port D1 high sink, O4 output, external interrupt; SWIM data interface, input pull-up during and after reset.
59 PD2/TIM3_CH1 bidirectional Port D2 high sink, O3 output, external interrupt; Timer 3 channel 1 (TIM2_CH3 via AFR1).
60 PD3/TIM2_CH2 bidirectional Port D3 high sink, O3 output, external interrupt; Timer 2 channel 2 (ADC_ETR via AFR0).
61 PD4/TIM2_CH1/BEEP bidirectional Port D4 high sink, O3 output, external interrupt; Timer 2 channel 1 (BEEP output via AFR7).
62 PD5/UART3_TX bidirectional Port D5 with external interrupt, O1 output; UART3 data transmit.
63 PD6/UART3_RX bidirectional Port D6 with external interrupt, O1 output; UART3 data receive (pulled up by ROM bootloader during activation).
64 PD7/TLI bidirectional Port D7 with external interrupt, O1 output; top level interrupt.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(14x14)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (incl. VDDA, VDDIO) VDDx - VSS -0.3 6.5 V 54
Input voltage on true open drain pins (PE1, PE2) VIN 6.5 V min printed as VSS - 0.3 54
Variations between different power pins /VDDx - VDD/ 50 mV 54
Variations between ground pins /VSSx - VSS/ 50 mV 54
Total current into VDD lines IVDD 60 mA source 55
Total current out of VSS lines IVSS 60 mA sink 55
Output current sunk by any I/O and control pin IIO 20 mA 55
Output current sourced by any I/O and control pin IIO 20 mA 55
Total output current sourced, devices with one VDDIO pin IIO 100 mA one VDDIO pin 55
Total output current sourced, devices with two VDDIO pins IIO 200 mA two VDDIO pins 55
Total output current sunk, devices with one VSSIO pin IIO 80 mA one VSSIO pin 55
Total output current sunk, devices with two VSSIO pins IIO 160 mA two VSSIO pins 55
Injected current on NRST pin IINJ(PIN) -4 4 mA 55
Injected current on OSCIN pin IINJ(PIN) -4 4 mA 55
Injected current on any other pin IINJ(PIN) -4 4 mA 55
Total injected current (sum of all I/O and control pins) IINJ(PIN) -20 20 mA 55
Storage temperature range TSTG -65 150 °C 55
Maximum junction temperature TJ 150 °C 55
ESD voltage, human body model VESD(HBM) 2000 V TA 25°C, JESD22-A114 89
ESD voltage, charge device model VESD(CDM) 1000 V TA 25°C, JESD22-C101 89
Internal CPU clock frequency fCPU 0 24 MHz TA ≤ 105 °C 56
Standard operating voltage VDD/VDD_IO 2.95 5.5 V 56
External capacitor on VCAP CEXT 470 3300 nF 56
ESR of external capacitor ESR 0.3 Ω at 1 MHz 56
ESL of external capacitor ESL 15 nH 56
Power dissipation PD 443 mW TA = 85 °C for suffix 6, 44/48/64/80-pin devices, 8 standard, 2 high sink and 2 open drain ports 56
Ambient temperature, 6 suffix TA -40 85 °C Maximum power dissipation 56
Junction temperature range, 6 suffix TJ -40 105 °C 6 suffix version 56
Power-on reset threshold VIT+ 2.65 2.8 2.95 V 57
Brown-out reset threshold VIT- 2.58 2.73 2.88 V 57
Brown-out reset hysteresis VHYS(BOR) 70 mV 57
Supply current in run mode, code from RAM IDD(RUN) 3.7 7.3 mA VDD = 5 V, fCPU = fMASTER = 24 MHz, TA ≤ 105 °C, HSE user ext. clock (24 MHz) 58
Supply current in run mode, code from RAM IDD(RUN) 2.5 3.4 mA VDD = 5 V, fCPU = fMASTER = 16 MHz, HSI RC osc. (16 MHz) 58
Supply current in run mode, code from Flash IDD(RUN) 10.8 18 mA VDD = 5 V, fCPU = fMASTER = 24 MHz, TA ≤ 105 °C, HSE user ext. clock (24 MHz) 58
Supply current in run mode, code from Flash IDD(RUN) 8.1 13.2 mA VDD = 5 V, fCPU = fMASTER = 16 MHz, HSI RC osc. (16 MHz) 58
Supply current in wait mode IDD(WFI) 1.8 4.7 mA VDD = 5 V, fCPU = fMASTER = 24 MHz, TA ≤ 105 °C, HSE user ext. clock (24 MHz) 60
Supply current in wait mode IDD(WFI) 1.2 1.6 mA VDD = 5 V, fCPU = fMASTER = 16 MHz, HSI RC osc. (16 MHz) 60
Supply current in halt mode, Flash in power-down mode, max at 85 °C IDD(H) 6.5 35 µA VDD = 5 V, Flash in power-down mode, HSI clock after wakeup, max at 85 °C 62
Supply current in halt mode, Flash in power-down mode, max at 125 °C IDD(H) 6.5 100 µA VDD = 5 V, Flash in power-down mode, HSI clock after wakeup, max at 125 °C 62
HSE user external clock frequency fHSE_ext 0 24 MHz 65
OSCIN input leakage current ILEAK_HSE -1 1 µA VSS < VIN < VDD 65
External high speed oscillator frequency fHSE 1 24 MHz 66
HSI frequency fHSI 16 MHz 67
HSI accuracy, factory calibrated ACCHSI -1.5 1.5 % VDD = 5 V, TA = 25 °C 67
HSI accuracy, factory calibrated ACCHSI -3 3 % 2.95 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C 67
LSI frequency fLSI 110 128 146 kHz 68
Flash/EEPROM operating voltage VDD 2.95 5.5 V fCPU ≤ 24 MHz 69
Standard programming time tprog 6 6.6 ms byte/word/block (1 byte/4 bytes/128 bytes) 69
Erase time for 1 block (128 bytes) terase 3 3.3 ms 69
Pull-up resistor Rpu 30 55 80 kΩ VDD = 5 V, VIN = VSS 70
Input leakage current, analog and digital Ilkg -1 1 µA VSS ≤ VIN ≤ VDD 70
Output low level, standard ports, 8 pins sunk VOL 2 V IIO = 10 mA, VDD = 5 V 72
Output high level, standard ports, 8 pins sourced VOH 2.8 V IIO = 10 mA, VDD = 5 V 72
Output low level, high sink ports, 8 pins sunk VOL 0.8 V IIO = 10 mA, VDD = 5 V 72
Output high level, high sink ports, 8 pins sourced VOH 4 V IIO = 10 mA, VDD = 5 V 72
NRST output low level voltage VOL(NRST) 0.5 V IOL = 2 mA 78
NRST pull-up resistor RPU(NRST) 30 55 80 kΩ 78
ADC clock frequency fADC 1 6 MHz VDDA = 4.5 to 5.5 V 85
ADC analog supply VDDA 3 5.5 V 85
Thermal resistance junction-ambient, LQFP 64 - 14 x 14 mm θJA 45 °C/W JEDEC JESD51-2, 4-layer PCB, natural convection 108

CAD (KiCad official)

  • Symbol: STM8S207RBT6C
  • Footprint: Package_QFP:LQFP-64_14x14mm_P0.8mm
  • 3D model: LQFP-64(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm8s207rbt6c-etched.step / stm8s207rbt6c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8s207rbt6c.step / stm8s207rbt6c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (117 pp, sha256 8a2a2138dc9cbe90, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF