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TPS386000QRGPRQ1
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Texas Instruments Supervisor And Reset ICs, QFN-20-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS386000QRGPRQ1
Texas Instruments · Supervisor And Reset ICs · QFN-20-EP(4x4)
TPS386000QRGPRQ1 from Texas Instruments, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Manual reset input for SVS-1; a logic-low level asserts RESET1 or RESET1, and the input range is 0 V to VDD with VIL of 0.3 × VDD maximum. |
| 2 | CT4 | passive | Reset delay programming pin for SVS-4; a 40 kΩ to 200 kΩ resistor to VDD or an open pin selects a fixed delay, while a capacitor above 220 pF to GND selects the programmable delay of 1.4 ms to 10 s. |
| 3 | CT3 | passive | Reset delay programming pin for SVS-3; a 40 kΩ to 200 kΩ resistor to VDD or an open pin selects a fixed delay, while a capacitor above 220 pF to GND selects the programmable delay of 1.4 ms to 10 s. |
| 4 | CT2 | passive | Reset delay programming pin for SVS-2; a 40 kΩ to 200 kΩ resistor to VDD or an open pin selects a fixed delay, while a capacitor above 220 pF to GND selects the programmable delay of 1.4 ms to 10 s. |
| 5 | CT1 | passive | Reset delay programming pin for SVS-1; a 40 kΩ to 200 kΩ resistor to VDD or an open pin selects a fixed delay, while a capacitor above 220 pF to GND selects the programmable delay of 1.4 ms to 10 s. |
| 6 | SENSE4H | input | Rising monitor voltage input to SVS-4; RESET4 or RESET4 is asserted when the voltage exceeds the positive threshold VIT+ (400 mV typical, 396 mV to 404 mV), and it can also monitor the negative rail together with VREF. |
| 7 | SENSE4L | input | Falling monitor voltage input to SVS-4; RESET4 or RESET4 is asserted when the voltage drops below the negative-going threshold VIT- (400 mV typical, 396 mV to 404 mV). |
| 8 | SENSE3 | input | Monitor voltage input to SVS-3; RESET3 is asserted when the voltage drops below the threshold VIT- (400 mV typical, 396 mV to 404 mV). |
| 9 | SENSE2 | input | Monitor voltage input to SVS-2; RESET2 is asserted when the voltage drops below the threshold VIT- (400 mV typical, 396 mV to 404 mV). |
| 10 | SENSE1 | input | Monitor voltage input to SVS-1; RESET1 is asserted when the voltage drops below the threshold VIT- (400 mV typical, 396 mV to 404 mV). |
| 11 | NC | unconnected | Not connected internally; TI recommends connecting this pin to the GND pin (pin 12) next to it. |
| 12 | GND | power_in | Ground reference pin for the device. |
| 13 | VREF | power_in | Reference voltage output (1.2 V) intended only to source current into resistor(s); do not connect only capacitors to it and do not connect resistors to a voltage higher than VREF. |
| 14 | VDD | power_in | Supply voltage with an allowed range of 1.8 V to 6.5 V; TI recommends a 0.1-µF ceramic capacitor placed close to this pin. |
| 15 | RESET1 | output | Active-low open-drain reset output of SVS-1 that stays in a low-impedance state while asserted and goes high-impedance after the delay set by CT1 once released. |
| 16 | RESET2 | output | Active-low open-drain reset output of SVS-2 that stays in a low-impedance state while asserted and goes high-impedance after the delay set by CT2 once released. |
| 17 | RESET3 | output | Active-low open-drain reset output of SVS-3 that stays in a low-impedance state while asserted and goes high-impedance after the delay set by CT3 once released. |
| 18 | RESET4 | output | Active-low open-drain reset output of SVS-4 that stays in a low-impedance state while asserted and goes high-impedance after the delay set by CT4 once released. |
| 19 | WDO | output | Open-drain watchdog timer output that goes to a low-impedance state to GND when the WDT times out and stays high-impedance otherwise. |
| 20 | WDI | input | Watchdog trigger input; a positive or negative logic edge every 610 ms (typical) prevents a WDT timeout, with the timer starting when RESET1 is released. |
| 21 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-20-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (recommended operating) | VDD | 1.8 | 6.5 | V | 5 | ||
| Operating free-air temperature | TA | -40 | 125 | °C | 5 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Reset delay programming pin voltage (CT1-CT4) | 0 | V | 5 | ||||
| Manual reset input voltage (MR) | 0 | V | 5 | ||||
| Watchdog timer trigger input voltage (WDI) | 0 | V | 5 | ||||
| Input supply voltage VDD (absolute maximum) | VDD | -0.3 | 7 | V | 4 | ||
| CT pin voltage (absolute maximum) | VCT1, VCT2, VCT3, VCT4 | -0.3 | V | Upper limit printed as VDD + 0.3 V | 4 | ||
| RESETn, RESETn, VMR, VSENSEn, VWDI, VWDO voltage (absolute maximum) | VRESET1, VRESET2, VRESET3, VRESET4, VMR, VSENSE1, VSENSE2, VSENSE3, VSENSE4L, VSENSE4H, VWDI, VWDO | -0.3 | 7 | V | 4 | ||
| RESETn, RESETn, WDO, WDO, VREF pin current (absolute maximum) | 5 | mA | 4 | ||||
| Operating virtual junction temperature (absolute maximum) | TJ | -40 | 150 | °C | 4 | ||
| Operating ambient temperature (absolute maximum) | TA | -40 | 125 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Input supply range | VDD | 1.8 | 6.5 | V | 5 | ||
| Supply current (current into VDD pin) | IDD | 11 | 19 | μA | VDD = 3.3 V, RESETn or RESETn not asserted, WDI toggling, no output load, VREF open | 5 | |
| Supply current (current into VDD pin) | IDD | 13 | 22 | μA | VDD = 6.5 V, RESETn or RESETn not asserted, WDI toggling, no output load, VREF open | 5 | |
| Negative-going input threshold voltage | VIT- | 396 | 400 | 404 | mV | SENSE1, SENSE2, SENSE3, SENSE4L | 5 |
| Positive-going input threshold voltage | VIT+ | 396 | 400 | 404 | mV | SENSE4H | 5 |
| Hysteresis (positive-going) on VIT- | VHYS- | 3.5 | 10 | mV | SENSE1, SENSE2, SENSE3, SENSE4L | 5 | |
| Hysteresis (negative-going) on VIT+ | VHYS+ | 3.5 | 10 | mV | SENSE4H | 5 | |
| Input current at SENSEm pin | ISENSE | -25 | 25 | nA | VSENSEm = 0.42 V | 5 | |
| CT1 pin charging current | ICT | 245 | 300 | 355 | nA | CCT1 > 220 pF, VCT1 = 0.5 V | 5 |
| CT2, CT3, CT4 pin charging current | ICT | 235 | 300 | 365 | nA | CCTn > 220 pF, VCTn = 0.5 V | 5 |
| CTn pin threshold | VTH(CTn) | 1.18 | 1.238 | 1.299 | V | CCTn > 220 pF | 5 |
| MR and WDI logic low input | VIL | 0 | V | Upper limit printed as 0.3 × VDD | 5 | ||
| Low-level RESETn or RESETn output voltage | VOL | 0.4 | V | IOL = 1 mA | 6 | ||
| Low-level RESETn or RESETn output voltage | VOL | 0.3 | V | SENSEn = 0 V, 1.3 V < VDD < 1.8 V, IOL = 0.4 mA | 6 | ||
| Low-level WDO output voltage | VOL | 0.4 | V | IOL = 1 mA | 6 | ||
| RESETn, RESETn, WDO, and WDO leakage current | ILKG | -300 | 300 | nA | VRESETn = 6.5 V, RESETn, RESETn, WDO, and WDO are logic high | 6 | |
| Reference voltage output | VREF | 1.18 | 1.2 | 1.22 | V | 1 μA < IVREF < 0.2 mA (source only, no sink) | 6 |
| RESETn delay time (CTn = Open) | tD | 14 | 20 | 24 | ms | CTn = Open | 6 |
| RESETn delay time (CTn = VDD) | tD | 225 | 300 | 375 | ms | CTn = VDD | 6 |
| Watchdog timer time-out period | tWDT | 450 | 600 | 750 | ms | 6 | |
| Junction-to-ambient thermal resistance | RθJA | 50.8 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 1.5 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 21 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ψJT | 42.8 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ψJB | 8.8 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 21.2 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
TPS386000QRGPRQ1 - Footprint:
Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm - 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
tps386000qrgprq1-etched.step/tps386000qrgprq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps386000qrgprq1.step/tps386000qrgprq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (35 pp, sha256
0e316f3c8098f3a4, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).