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XD74LS193

Public Made by Adom

by adom

XINLUDA Counters, Dividers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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XD74LS193

XINLUDA · Counters, Dividers · DIP-16

XD74LS193 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 B input Preset data input B, loaded into flip-flop QB while LOAD is low.
2 QB output Flip-flop B output of the counter.
3 QA output Flip-flop A output of the counter.
4 DOWN input Count-down clock input, triggered on a low-to-high transition while UP is high.
5 UP input Count-up clock input, triggered on a low-to-high transition while DOWN is high.
6 QC output Flip-flop C output of the counter.
7 QD output Flip-flop D output of the counter.
8 GND power_in Ground.
9 D input Preset data input D, loaded into flip-flop QD while LOAD is low.
10 C input Preset data input C, loaded into flip-flop QC while LOAD is low.
11 LOAD input Active-low load input; presets the outputs to the data inputs independently of the count pulses.
12 CO output Active-low carry output; pulses with width equal to the count-up input on overflow, feeds the UP input of the next counter.
13 BO output Active-low borrow output; pulses with width equal to the count-down input on underflow, feeds the DOWN input of the next counter.
14 CLR input Clear input; a high level forces all outputs low independently of count and load inputs.
15 A input Preset data input A, loaded into flip-flop QA while LOAD is low.
16 VCC power_in Supply voltage, recommended 4.75 V to 5.25 V (7 V absolute maximum).

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.75 5 5.25 V 6
High-level output current IOH -400 μA 6
Low-level output current IOL 8 mA 6
Clock frequency fclock 0 25 MHz 6
Width of any input pulse tw 20 ns 6
Clear inactive-state setup time tsu 15 ns 6
Load inactive-state setup time tsu 15 ns 6
Data setup time tsu 20 ns 6
Data hold time th 5 ns 6
Operating free-air temperature range TA 0 70 °C 6
Supply voltage VCC 7 V 5
Input voltage (74LS192, 74LS193) VI 7 V 5
Operating free-air temperature range (DIP package) TA 0 70 °C 5
Storage temperature range Tstg -65 150 °C 5
High-level input voltage VIH 2 V 6
Low-level input voltage VIL 0.8 V 6
Input clamp voltage VIK -1.5 V VCC = MIN, II = −18 mA 6
High-level output voltage VOH 2.7 3.4 V VCC = MIN, VIL = VIL MAX, VIH = 2 V, IOH = −400 μA 6
Low-level output voltage VOL 0.15 0.4 V VCC = MIN, VIH = 2 V, VIL = VIL MAX, IOL = 4 mA 6
Low-level output voltage VOL 0.35 0.5 V VCC = MIN, VIH = 2 V, VIL = VIL MAX, IOL = 8 mA 6
Input current at maximum input voltage II 0.1 mA VCC = MAX, VI = 7 V 6
High-level input current IIH 20 μA VCC = MAX, VI = 2.7 V 6
Low-level input current IIL -0.4 mA VCC = MAX, VI = 0.4 V 6
Short-circuit output current IOS -20 -100 mA VCC = MAX 6
Supply current ICC 19 34 mA VCC = MAX 6
Maximum clock frequency fMAX 25 32 MHz VCC = 5 V, TA = 25°C 7
Propagation delay low-to-high, UP/DOWN to CO/BO tPLH 17 26 ns VCC = 5 V, TA = 25°C; from UP to CO 7
Propagation delay high-to-low, UP to CO tPHL 18 24 ns VCC = 5 V, TA = 25°C; from UP to CO 7
Propagation delay low-to-high, DOWN to BO tPLH 16 24 ns VCC = 5 V, TA = 25°C; from DOWN to BO 7
Propagation delay high-to-low, DOWN to BO tPHL 15 24 ns VCC = 5 V, TA = 25°C; from DOWN to BO 7
Propagation delay low-to-high, UP or DOWN to Q tPLH 27 38 ns VCC = 5 V, TA = 25°C, CL = 15 pF, RL = 2 k 7
Propagation delay high-to-low, UP or DOWN to Q tPHL 30 47 ns VCC = 5 V, TA = 25°C, CL = 15 pF, RL = 2 k 7
Propagation delay low-to-high, LOAD to Q tPLH 24 40 ns VCC = 5 V, TA = 25°C 7
Propagation delay high-to-low, LOAD to Q tPHL 25 40 ns VCC = 5 V, TA = 25°C 7
Propagation delay high-to-low, CLR to Q tPHL 23 35 ns VCC = 5 V, TA = 25°C 7

CAD (KiCad official)

  • Symbol: XD74LS193
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: xd74ls193-etched.step / xd74ls193-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls193.step / xd74ls193.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (8 pp, sha256 d5b332dca46f6938, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF