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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

R7F123FMG4AFB-C#AA0

RENESAS · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

R7F123FMG4AFB-C#AA0 from RENESAS, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P120	bidirectional	Port 12 I/O (EVDD0 domain) with ANI25, TI07/TO07, TRDIOD0, SO01, (SCK10), INTP4 alternates.
2	P47	bidirectional	Port 4 I/O with INTP13 alternate.
3	P46	bidirectional	Port 4 I/O with (TI12)/(TO12) alternates.
4	P45	bidirectional	Port 4 I/O with (TI10)/(TO10) alternates.
5	P44	bidirectional	Port 4 I/O with (TI07)/(TO07) alternates.
6	P43	bidirectional	Port 4 I/O with (LRXD0) alternate; input threshold level selectable.
7	P42	bidirectional	Port 4 I/O with (LTXD0) alternate.
8	P41	bidirectional	Port 4 I/O with TI10/TO10, TRJIO0, TRD0RES, (SI10), (RXD1), SNZOUT2 alternates; input threshold level selectable.
9	P40/TOOL0	bidirectional	Port 4 I/O and data I/O for flash programmer/debugger; must be pulled up externally when on-chip debugging is enabled, and EVDD at reset release selects normal mode (0 V selects flash programming mode).
10	RESET	input	Active-low external system reset input; connect to VDD directly or via a resistor when unused.
11	P124/XT2/EXCLKS	input	Input port, subsystem clock resonator connection XT2 or external subsystem clock input; do not use XT1/XT2 functions in grade-5 products.
12	P123/XT1	input	Input port or subsystem clock resonator connection XT1; do not use in grade-5 products.
13	P137/INTP0	input	Input-only port with INTP0 external interrupt input (VDD domain).
14	P122/X2/EXCLK	input	Input port, main system clock resonator connection X2 or external clock input EXCLK.
15	P121/X1	input	Input port or main system clock resonator connection X1.
16	REGC	passive	Regulator output stabilization capacitor pin; connect to VSS via a 0.47 to 1 µF capacitor.
17	VSS	power_in	Ground for P33, P34, P80-P87, P90-P97, P121-P124, P137, RESET and non-port pins.
18	EVSS0	power_in	Ground for port pins not powered by VSS.
19	VDD	power_in	Positive supply for P33, P34, P80-P87, P90-P97, P121-P124, P137, RESET and non-port pins.
20	EVDD0	power_in	Positive supply for port pins not powered by VDD.
21	P60	bidirectional	Port 6 I/O with (TO01), (SCK00), (SCL00); N-ch open-drain output selectable.
22	P61	bidirectional	Port 6 I/O with (TO02), (SI00), (SDA00), (RXD0); N-ch open-drain output selectable.
23	P62	bidirectional	Port 6 I/O with (TO03), (SO00), (TXD0), SCLA0 (IICA0 clock); TTL input selectable.
24	P63	bidirectional	Port 6 I/O with (TO07), (SSI00), SDAA0 (IICA0 data); TTL input selectable.
25	P64	bidirectional	Port 6 I/O with (SNZOUT3) alternate.
26	P65	bidirectional	Port 6 I/O with (SNZOUT2) alternate.
27	P66	bidirectional	Port 6 I/O with (TI00)/(TO00) alternates.
28	P67	bidirectional	Port 6 I/O with (TI02)/(TO02) alternates.
29	P00	bidirectional	Port 0 I/O with (TI05)/(TO05), INTP9 alternates.
30	P140	bidirectional	Port 14 I/O with TRD1RES and PCLBUZ0 clock/buzzer output.
31	P130/RESOUT	output	Output-only port 13 and reset output RESOUT.
32	P77	bidirectional	Port 7 I/O with (SSI10), INTP12, KR7 key interrupt input.
33	P76	bidirectional	Port 7 I/O with (SCK10) and KR6 key interrupt input.
34	P75	bidirectional	Port 7 I/O with (SI10), (RXD1), KR5 key interrupt input.
35	P74	bidirectional	Port 7 I/O with ANI30 analog input, (SO10), (TXD1), KR4.
36	P73	bidirectional	Port 7 I/O with ANI29 analog input, SSI11, SNZOUT7, KR3.
37	P72	bidirectional	Port 7 I/O with ANI28 analog input, SO11, SNZOUT6, KR2.
38	P71	bidirectional	Port 7 I/O with ANI27 analog input, SCK11/SCL11, INTP6, SNZOUT5, KR1.
39	P70	bidirectional	Port 7 I/O with ANI26 analog input, SI11/SDA11, INTP8, SNZOUT4, KR0.
40	P32	bidirectional	Port 3 I/O with (SO11) and INTP7; N-ch open-drain output selectable.
41	P30	bidirectional	Port 3 I/O with TI01/TO01, TRDIOD1, SSI00, INTP2, SNZOUT0; TTL input selectable.
42	P17	bidirectional	Port 1 I/O with TI00/TO00, TRDIOB1, SCK00/SCL00, INTP3.
43	P16	bidirectional	Port 1 I/O with TI02/TO02, TRDIOC1, SI00/SDA00, RXD0, TOOLRXD.
44	P15	bidirectional	Port 1 I/O with TI05/TO05, TRDIOA1, SO00, TXD0, RTC1HZ, TOOLTXD.
45	P31	bidirectional	Port 3 I/O with STOPST output and (INTP2).
46	P50	bidirectional	Port 5 I/O with (SSI01) and (INTP3).
47	P51	bidirectional	Port 5 I/O with (SO01) and INTP11.
48	P52	bidirectional	Port 5 I/O with (SCK01) and (STOPST).
49	P53	bidirectional	Port 5 I/O with (SI01) and INTP10.
50	P14	bidirectional	Port 1 I/O with TI06/TO06, TRDIOC0, SCK01/SCL01, LRXD0.
51	P13	bidirectional	Port 1 I/O with TI04/TO04, TRDIOA0, TRDCLK0, SI01/SDA01, LTXD0.
52	P12	bidirectional	Port 1 I/O with TI11/TO11, (TRDIOD0), INTP5, SO10, TXD1, SNZOUT3.
53	P11	bidirectional	Port 1 I/O with TI12/TO12, (TRDIOB0), SI10/SDA10, RXD1.
54	P10	bidirectional	Port 1 I/O with TI13/TO13, TRJO0, SCK10/SCL10.
55	P54	bidirectional	Port 5 I/O with (TI11)/(TO11) and SSI10; TTL input selectable.
56	P55	bidirectional	Port 5 I/O with (TI13)/(TO13).
57	P56	bidirectional	Port 5 I/O with (SNZOUT1).
58	P57	bidirectional	Port 5 I/O with (SNZOUT0).
59	P33	bidirectional	Port 3 I/O (VDD domain) with AVREFP A/D positive reference input and ANI6 analog input.
60	P34	bidirectional	Port 3 I/O (VDD domain) with AVREFM A/D negative reference input and ANI7 analog input.
61	P80	bidirectional	Port 8 I/O with ANI0 analog input.
62	P81	bidirectional	Port 8 I/O with ANI1 analog input.
63	P82	bidirectional	Port 8 I/O with ANI2 analog input.
64	P83	bidirectional	Port 8 I/O with ANI3 analog input.
65	P84	bidirectional	Port 8 I/O with ANI4 analog input.
66	P85	bidirectional	Port 8 I/O with ANI5 analog input.
67	P86	bidirectional	Port 8 I/O with ANI8 analog input.
68	P87	bidirectional	Port 8 I/O with ANI9 analog input.
69	P90	bidirectional	Port 9 I/O with ANI10 analog input.
70	P91	bidirectional	Port 9 I/O with ANI11 analog input.
71	P92	bidirectional	Port 9 I/O with ANI12 analog input.
72	P93	bidirectional	Port 9 I/O with ANI13 analog input.
73	P94	bidirectional	Port 9 I/O with ANI14 analog input.
74	P95	bidirectional	Port 9 I/O with ANI15 analog input.
75	P96	bidirectional	Port 9 I/O with ANI16 analog input (normal-speed).
76	P97	bidirectional	Port 9 I/O with ANI17 analog input (normal-speed).
77	P02	bidirectional	Port 0 I/O with (TI06)/(TO06).
78	P126	bidirectional	Port 12 I/O with (TI01)/(TO01).
79	P01	bidirectional	Port 0 I/O with (TI04)/(TO04).
80	P125	bidirectional	Port 12 I/O with ANI24, TI03/TO03, TRDIOB0, SSI01, INTP1, SNZOUT1; TTL input selectable.

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	LQFP-80(12x12)
Category	Embedded Processors & Controllers
Pins	80

CAD (KiCad official)

Symbol: R7F123FMG4AFB-C#AA0
Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
3D model files: r7f123fmg4afb-c-aa0-etched.step / r7f123fmg4afb-c-aa0-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); r7f123fmg4afb-c-aa0.step / r7f123fmg4afb-c-aa0.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (2045 pp, sha256 a2bdc3bd129ad7cf, retrieved 2026-10-21, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF