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Contents

README

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STM8L151K6T3

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

STM8L151K6T3 from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NRST/PA1 bidirectional Active-low reset input with pull-up at power-up (RPU 30 to 60 kΩ); as PA1 it can only be configured as open-drain or push-pull output, not as a general-purpose input.
2 PA2 bidirectional Port A2 with HSE oscillator input (OSC_IN); 3.6 V tolerant I/O with high sink/source (20 mA) capability; USART1_TX and SPI1_MISO are remap options.
3 PA3 bidirectional Port A3 with HSE oscillator output (OSC_OUT); 3.6 V tolerant I/O with high sink/source (20 mA) capability; USART1_RX and SPI1_MOSI are remap options.
4 PA4 bidirectional Port A4 with Timer 2 break input (TIM2_BKIN), ADC1 input 2 (ADC1_IN2) and comparator 1 positive input (COMP1_INP); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
5 PA5 bidirectional Port A5 with Timer 3 break input (TIM3_BKIN), ADC1 input 1 (ADC1_IN1) and comparator 1 positive input (COMP1_INP); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
6 PA6 bidirectional Port A6 with ADC1 input 0 (ADC1_IN0) and comparator 1 positive input (COMP1_INP); ADC1 trigger is available as a remap option; 3.6 V tolerant I/O with high sink/source (20 mA) capability.
7 VSS1/VSSA/VREF- power_in I/O ground, analog ground and ADC1 negative voltage reference.
8 VDD1/VDDA/VREF+ power_in Digital power supply, analog supply and ADC1 positive voltage reference; the device operates from 1.8 V to 3.6 V (down to 1.65 V at power down).
9 PD0 bidirectional Port D0 with Timer 3 channel 2 (TIM3_CH2), ADC1 input 22 (ADC1_IN22) and comparator 1 and 2 positive inputs; 3.6 V tolerant I/O, and this pin function is available on STM8L151xx devices only.
10 PD1 bidirectional Port D1 with Timer 1 inverted channel 3 (TIM1_CH3N), ADC1 input 21 (ADC1_IN21) and comparator 1 and 2 positive inputs; 3.6 V tolerant I/O with high sink/source (20 mA) capability.
11 PD2 bidirectional Port D2 with Timer 1 channel 1 (TIM1_CH1), ADC1 input 20 (ADC1_IN20) and comparator 1 positive input (COMP1_INP); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
12 PD3 bidirectional Port D3 with Timer 1 external trigger (TIM1_ETR), ADC1 input 19 (ADC1_IN19) and comparator 1 positive input (COMP1_INP); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
13 PB0 bidirectional Port B0 with Timer 2 channel 1 (TIM2_CH1), ADC1 input 18 (ADC1_IN18) and comparator 1 positive input (COMP1_INP); a pull-up is applied during reset and the pin is floating input after reset release, 3.6 V tolerant with high sink/source (20 mA) capability.
14 PB1 bidirectional Port B1 with Timer 3 channel 1 (TIM3_CH1), ADC1 input 17 (ADC1_IN17) and comparator 1 positive input (COMP1_INP); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
15 PB2 bidirectional Port B2 with Timer 2 channel 2 (TIM2_CH2), ADC1 input 16 (ADC1_IN16) and comparator 1 positive input (COMP1_INP); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
16 PB3 bidirectional Port B3 with Timer 2 external trigger (TIM2_ETR, remap), Timer 1 inverted channel 2 (TIM1_CH2N), ADC1 input 15 (ADC1_IN15) and comparator 1 positive input (COMP1_INP); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
17 PB4 bidirectional Port B4 with SPI1 master/slave select (SPI1_NSS, remap), ADC1 input 14 (ADC1_IN14), DAC output (DAC_OUT) and comparator 1 positive input (COMP1_INP); a pull-up is applied during reset and the pin is floating input after reset release.
18 PB5 bidirectional Port B5 with SPI1 clock (SPI1_SCK, remap), ADC1 input 13 (ADC1_IN13), DAC output (DAC_OUT) and comparator 1 positive input (COMP1_INP); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
19 PB6 bidirectional Port B6 with SPI1 master out/slave in (SPI1_MOSI, remap), ADC1 input 12 (ADC1_IN12), DAC output (DAC_OUT) and comparator 1 positive input (COMP1_INP); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
20 PB7 bidirectional Port B7 with SPI1 master in/slave out (SPI1_MISO, remap), ADC1 input 11 (ADC1_IN11) and comparator 1 positive input (COMP1_INP); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
21 PD4 bidirectional Port D4 with Timer 1 channel 2 (TIM1_CH2), ADC1 input 10 (ADC1_IN10) and comparator 1 positive input (COMP1_INP); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
22 PD5 bidirectional Port D5 with Timer 1 channel 3 (TIM1_CH3), ADC1 input 9 (ADC1_IN9) and comparator 1 positive input (COMP1_INP); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
23 PD6 bidirectional Port D6 with Timer 1 break input (TIM1_BKIN), ADC1 input 8 (ADC1_IN8), RTC calibration (RTC_CALIB), internal voltage reference output (VREFINT) and comparator 1 positive input (COMP1_INP); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
24 PD7 bidirectional Port D7 with Timer 1 inverted channel 1 (TIM1_CH1N), ADC1 input 7 (ADC1_IN7), RTC alarm (RTC_ALARM), internal voltage reference output (VREFINT) and comparator 1 positive input (COMP1_INP); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
25 PC0 bidirectional Port C0 with I2C1 data (I2C1_SDA); 5 V tolerant I/O configured as true open-drain (no protection diode to VDD).
26 PC1 bidirectional Port C1 with I2C1 clock (I2C1_SCL); 5 V tolerant I/O configured as true open-drain (no protection diode to VDD).
27 PC2 bidirectional Port C2 with USART1 receive (USART1_RX), ADC1 input 6 (ADC1_IN6), comparator 1 positive input (COMP1_INP) and internal voltage reference output (VREFINT); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
28 PC3 bidirectional Port C3 with USART1 transmit (USART1_TX), ADC1 input 5 (ADC1_IN5), comparator 1 positive input (COMP1_INP) and comparator 2 negative input (COMP2_INM); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
29 PC4 bidirectional Port C4 with USART1 synchronous clock (USART1_CK), I2C1_SMB, configurable clock output (CCO), ADC1 input 4 (ADC1_IN4), comparator 2 negative input (COMP2_INM) and comparator 1 positive input (COMP1_INP); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
30 PC5 bidirectional Port C5 with LSE oscillator input (OSC32_IN), SPI1 master/slave select (SPI1_NSS, remap) and USART1 transmit (USART1_TX, remap); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
31 PC6 bidirectional Port C6 with LSE oscillator output (OSC32_OUT), SPI1 clock (SPI1_SCK, remap) and USART1 receive (USART1_RX, remap); 3.6 V tolerant I/O with high sink/source (20 mA) capability.
32 PA0 bidirectional Port A0 with USART1 synchronous clock (USART1_CK, remap), SWIM input and output, beep output (BEEP) and infrared timer output (IR_TIM); high sink LED driver capability, and the pin is in input pull-up during reset and after reset release.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-32(7x7)
Category Embedded Processors & Controllers
Pins 32

CAD (KiCad official)

  • Symbol: STM8L151K6T3
  • Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
  • 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm8l151k6t3-etched.step / stm8l151k6t3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8l151k6t3.step / stm8l151k6t3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (141 pp, sha256 76f669f0972e887a, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF