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STC15F2K60S2-28I-LQFP32
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STC Micro Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSTC15F2K60S2-28I-LQFP32
STC Micro · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)
STC15F2K60S2-28I-LQFP32 from STC Micro, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.0/ADC0/CCP1/RxD2 | bidirectional | Standard quasi-bidirectional I/O (P1.0) that can also serve as ADC channel 0, CCP1 capture/PWM output, or UART2 receive; each I/O drives up to 20mA and the whole chip must not exceed 90mA for this 32-pin package. |
| 2 | P1.1/ADC1/CCP0/TxD2 | bidirectional | Standard I/O (P1.1) that can also serve as ADC channel 1, CCP0 capture/PWM output, or UART2 transmit; each I/O drives up to 20mA and the whole chip must not exceed 90mA. |
| 3 | P1.2/ADC2/SS/ECI | bidirectional | Standard I/O (P1.2) that can also serve as ADC channel 2, the SPI slave select input, or the CCP/PCA external counter input ECI; each I/O drives up to 20mA. |
| 4 | P1.3/ADC3/MOSI | bidirectional | Standard I/O (P1.3) that can also serve as ADC channel 3 or the SPI master-out/slave-in line; each I/O drives up to 20mA. |
| 5 | P1.4/ADC4/MISO | bidirectional | Standard I/O (P1.4) that can also serve as ADC channel 4 or the SPI master-in/slave-out line; each I/O drives up to 20mA. |
| 6 | P1.5/ADC5/SCLK | bidirectional | Standard I/O (P1.5) that can also serve as ADC channel 5 or the SPI serial clock; each I/O drives up to 20mA. |
| 7 | P1.6/ADC6/RxD_3/XTAL2 | bidirectional | Standard I/O (P1.6) that can also serve as ADC channel 6, UART1 alternate receive (RxD_3), or the XTAL2 crystal output; when a external clock source is used this pin may be left floating. |
| 8 | P1.7/ADC7/TxD_3/XTAL1 | bidirectional | Standard I/O (P1.7) that can also serve as ADC channel 7, UART1 alternate transmit (TxD_3), or the XTAL1 crystal/clock input; when an external clock source is used this pin is its input. |
| 9 | P5.4/RST/MCLKO | bidirectional | Standard I/O (P5.4) that is I/O by default but can be set via STC-ISP as the active-high reset input RST, or as the MCLKO master clock output (MCLK/1, /2 or /4). |
| 10 | Vcc | power_in | Positive supply pin; the datasheet gives an operating range of 5.5V to 4.5V for the F-series (5V) part. |
| 11 | P5.5 | bidirectional | Standard I/O (P5.5) with no alternate function on this package, usable as a general-purpose port pin. |
| 12 | Gnd | power_in | Ground / negative supply pin. |
| 13 | P3.0/RxD/INT4/T2CLKO | bidirectional | Standard I/O (P3.0) that can also serve as UART1 receive (RxD), external interrupt INT4 (falling edge only, supports power-down wake-up), or the T2 clock output T2CLKO. |
| 14 | P3.1/TxD/T2 | bidirectional | Standard I/O (P3.1) that can also serve as UART1 transmit (TxD) or the external input of Timer/Counter 2 (T2). |
| 15 | P3.2/INT0 | bidirectional | Standard I/O (P3.2) that can also serve as external interrupt 0; INT0 can trigger on rising or falling edge (falling only if IT0 is set) and supports power-down wake-up. |
| 16 | P3.3/INT1 | bidirectional | Standard I/O (P3.3) that can also serve as external interrupt 1; INT1 can trigger on rising or falling edge (falling only if IT1 is set) and supports power-down wake-up. |
| 17 | P3.4/T0/T1CLKO/ECI_2 | bidirectional | Standard I/O (P3.4) that can also serve as the external input of Timer 0 (T0), the Timer 1 clock output T1CLKO, or the CCP/PCA external counter input ECI_2. |
| 18 | P3.5/T1/T0CLKO/CCP0_2 | bidirectional | Standard I/O (P3.5) that can also serve as the external input of Timer 1 (T1), the Timer 0 clock output T0CLKO, or CCP0 capture/PWM output on alternate pin CCP0_2. |
| 19 | P3.6/INT2/RxD_2/CCP1_2 | bidirectional | Standard I/O (P3.6) that can also serve as external interrupt INT2 (falling edge only, supports power-down wake-up), UART1 alternate receive RxD_2, or CCP1 on alternate pin CCP1_2. |
| 20 | P3.7/INT3/TxD_2/CCP2/CCP2_2 | bidirectional | Standard I/O (P3.7) that can also serve as external interrupt INT3 (falling edge only, supports power-down wake-up), UART1 alternate transmit TxD_2, or CCP2 on pins CCP2/CCP2_2. |
| 21 | P2.0/A8/RSTOUT_LOW | bidirectional | Standard I/O (P2.0) that can also serve as address bus bit A8 or the RSTOUT_LOW output, which is driven low after power-on and during reset. |
| 22 | P2.1/A9/SCLK_2 | bidirectional | Standard I/O (P2.1) that can also serve as address bus bit A9 or the SPI clock on alternate pin SCLK_2. |
| 23 | P2.2/A10/MISO_2 | bidirectional | Standard I/O (P2.2) that can also serve as address bus bit A10 or the SPI master-in/slave-out on alternate pin MISO_2. |
| 24 | P2.3/A11/MOSI_2 | bidirectional | Standard I/O (P2.3) that can also serve as address bus bit A11 or the SPI master-out/slave-in on alternate pin MOSI_2. |
| 25 | P2.4/A12/ECI_3/SS_2 | bidirectional | Standard I/O (P2.4) that can also serve as address bus bit A12, the CCP/PCA external counter input ECI_3, or the SPI slave select on alternate pin SS_2. |
| 26 | P2.5/A13/CCP0_3 | bidirectional | Standard I/O (P2.5) that can also serve as address bus bit A13 or CCP0 capture/PWM output on alternate pin CCP0_3. |
| 27 | P2.6/A14/CCP1_3 | bidirectional | Standard I/O (P2.6) that can also serve as address bus bit A14 or CCP1 capture/PWM output on alternate pin CCP1_3. |
| 28 | P2.7/A15/CCP2_3 | bidirectional | Standard I/O (P2.7) that can also serve as address bus bit A15 or CCP2 capture/PWM output on alternate pin CCP2_3. |
| 29 | P0.0/AD0 | bidirectional | Port 0 bit 0 that operates as a standard I/O or as the multiplexed low address/data bus bit AD0 when external bus access is used; not an ADC input. |
| 30 | P0.1/AD1 | bidirectional | Port 0 bit 1 that operates as a standard I/O or as the multiplexed low address/data bus bit AD1 when external bus access is used; not an ADC input. |
| 31 | P0.2/AD2 | bidirectional | Port 0 bit 2 that operates as a standard I/O or as the multiplexed low address/data bus bit AD2 when external bus access is used; not an ADC input. |
| 32 | P0.3/AD3 | bidirectional | Port 0 bit 3 that operates as a standard I/O or as the multiplexed low address/data bus bit AD3 when external bus access is used; not an ADC input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | TST | -55 | 125 | ℃ | 1374 | ||
| Operating temperature (I) | TA | -40 | 85 | ℃ | 1374 | ||
| DC power supply (5V) | VDD - VSS | -0.3 | 5.5 | V | 1374 | ||
| Voltage on any pin | -0.3 | V | 1374 | ||||
| VDD Operating Voltage | VDD | 3.3 | 5 | 5.5 | V | 1374 | |
| Power Down Current | IPD | 0.1 | uA | 5V | 1374 | ||
| Operating Current | ICC | 4 | 20 | mA | 5V | 1374 | |
| Input Low (P0,P1,P2,P3) | VIL1 | 0.8 | V | 5V | 1374 | ||
| Input High (P0,P1,P2,P3) | VIH1 | 2 | V | 5V | 1374 | ||
| Input High (RESET) | VIH2 | 2.2 | V | 5V | 1374 | ||
| Sourcing Current for output high (P0,P1,P2,P3) (Quasi-output) | IOH1 | 200 | 270 | uA | 5V | 1374 | |
| Logic 0 input current (P0,P1,P2,P3) | IIL | 50 | uA | Vpin=0V | 1374 | ||
| Logic 1 to 0 transition current (P0,P1,P2,P3) | ITL | 100 | 270 | 600 | uA | Vpin=2.0V | 1374 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the | 524 |
CAD (KiCad official)
- Symbol:
STC15F2K60S2-28I-LQFP32 - Footprint:
Package_QFP:LQFP-32_7x7mm_P0.8mm - 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files:
stc15f2k60s2-28i-lqfp32-etched.step/stc15f2k60s2-28i-lqfp32-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stc15f2k60s2-28i-lqfp32.step/stc15f2k60s2-28i-lqfp32.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STC Micro datasheet (1473 pp, sha256
c1fab41b0006cc18, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).