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PB7170P48

Public Made by Adom

by adom

PST Battery Management, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)pb7170p48factory-2.0.0extractor-text
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Contents

README

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PB7170P48

PST · Battery Management · LQFP-48(7x7)

PB7170P48 from PST, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PVDD power_in High-voltage DC supply positive input, connected to the highest voltage point of the measured cells (abs max 88V, recommended 12-80V relative to PGND).
2 C17 input Positive connection of cell 17.
3 C16 input Positive connection of cell 16 and negative connection of cell 17.
4 C15 input Positive connection of cell 15 and negative connection of cell 16.
5 C14 input Positive connection of cell 14 and negative connection of cell 15.
6 C13 input Positive connection of cell 13 and negative connection of cell 14.
7 C12 input Positive connection of cell 12 and negative connection of cell 13.
8 C11 input Positive connection of cell 11 and negative connection of cell 12.
9 C10 input Positive connection of cell 10 and negative connection of cell 11.
10 C9 input Positive connection of cell 9 and negative connection of cell 10.
11 C8 input Positive connection of cell 8 and negative connection of cell 9.
12 C7 input Positive connection of cell 7 and negative connection of cell 8.
13 C6 input Positive connection of cell 6 and negative connection of cell 7.
14 C5 input Positive connection of cell 5 and negative connection of cell 6.
15 C4 input Positive connection of cell 4 and negative connection of cell 5.
16 C3 input Positive connection of cell 3 and negative connection of cell 4.
17 C2 input Positive connection of cell 2 and negative connection of cell 3.
18 C1 input Positive connection of cell 1 and negative connection of cell 2.
19 C0 input Negative connection of cell 1.
20 PGND power_in High-voltage DC supply negative input, connected to the lowest voltage point of the measured cells.
21 SRP input Positive input of the current-sense resistor (connected to PGND); differential SRP-SRN recommended range is ±230mV.
22 SRN input Negative input of the current-sense resistor; resistance to PGND should be kept below 1kΩ so common-mode stays under 2V.
23 DSG output Discharge MOSFET gate drive, typically 10V (8-13V).
24 PREMOS output Pre-charge/pre-discharge MOSFET gate drive, typically 10V (8-13V).
25 CHG output Charge MOSFET gate drive, typically 10V (8-13V).
26 LODD input Load detection input with 100kΩ internal pull-down; detection threshold 1V min to 1.7V max.
27 CHGD input Charger detection input with 2.8MΩ internal pull-down; detection voltage -950mV to -500mV.
28 AGND power_in Internal analog ground.
29 VREF power_in Internal ADC reference voltage output; needs an external decoupling capacitor to AGND (1uF recommended).
30 AVDD power_out 5V analog supply output; needs an external decoupling capacitor to AGND (1uF recommended).
31 VAA power_out 5V external-measurement supply output, usable to bias thermistor divider networks.
32 AUXIN5 input Auxiliary measurement input 5 for temperature or other sensor analog output (0.5-4.5V recommended).
33 AUXIN4 input Auxiliary measurement input 4 for temperature or other sensor analog output (0.5-4.5V recommended).
34 AUXIN3 input Auxiliary measurement input 3 for temperature or other sensor analog output (0.5-4.5V recommended).
35 AUXIN2 input Auxiliary measurement input 2 for temperature or other sensor analog output (0.5-4.5V recommended).
36 AUXIN1 input Auxiliary measurement input 1 for temperature or other sensor analog output (0.5-4.5V recommended).
37 DRIVE output Drive output of 4V/5.7V to the base of an external NPN transistor to obtain 3.3V/5V at the emitter for external circuits in low-power mode.
38 ACT input Chip activation pin, active high, with internal 8MΩ pull-up and external capacitor to ground; shorting to ground forces ultra-low-power shutdown mode.
39 DVDD power_out 3.3V digital supply output; needs an external decoupling capacitor to DGND.
40 ALERT bidirectional Active-low open-drain interrupt output that also serves as external protection input; external pull-down triggers external protection, needs an external pull-up (4.7k recommended).
41 PROG input Connect to DGND.
42 GPIO1 bidirectional General-purpose input/output 1.
43 GPIO0 bidirectional General-purpose input/output 0.
44 SDO output SPI slave data output; 47K resistor to ground recommended in pin table.
45 SDI input SPI slave data input.
46 CSN input SPI slave chip select, active low; pulling low wakes the AFE from sleep.
47 SCLK input SPI slave clock input.
48 DGND power_in Digital supply ground.

Key specifications

Parameter Value
Manufacturer PST
Package LQFP-48(7x7)
Category Power Management (PMIC)
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
PVDD to PGND voltage VPVDD-VPGND -0.5 88 V PVDD 9
Cell voltage VCn-VCn-1 -0.5 10 V n=1-17 9
AUXIN input voltage VAUXIN-VAGND -0.5 5.5 V 9
Current sense voltage VSRP-VSRN -500 500 mV 9
MOS drive output -0.5 20 V CHG, DSG, PREMOS 9
DRIVE output -0.5 10 V 9
Digital signals -0.5 5.5 V CSN, SDI, SDO, SCLK, ALERT, GPIO0, GPIO1, PROG 9
Other ports -0.5 5.5 V DVDD, AVDD, ACT, VAA, VREF, CHGD, LODD, SPR, SRN 9
Internal balance current 150 mA single CELL 9
Operating temperature (abs max) -40 125 °C 9
Storage temperature -65 150 °C 9
Soldering temperature 300 °C duration 10S 9
ESD HBM 2 kV 9
ESD CDM 500 V 9
Total supply voltage VPVDD-VPGND 12 80 V 9
Cell voltage VCn-VCn-1 -0.5 5 V n=1-17 9
AUXIN input voltage VAUXIN-VAGND 0.5 4.5 V 9
Current input VSRP-VSRN -230 230 mV 9
MOS drive output 0 13 V CHG, DSG, PREMOS 9
Digital input 0 3.6 V CSN, SDI, SCLK, ALERT 9
Digital output 0 3.6 V SDO, GPIO0, GPIO1, ALERT 9
Internal balance current 100 mA single CELL 9
Operating temperature -20 85 °C 9
VADC measurement range VRANGE -0.5 5 V 10
VADC accuracy ACC1 -2 2 mV TA=25°C Vcell=3.6V 10
VADC accuracy ACC1 -5 5 mV -20~85°C 10
VADC accuracy ACC1 -10 10 mV -40~125°C 10
Fast current measurement range CRANGE -300 300 mV 10
Fast current accuracy CACC -1 1 mV 10
CADC measurement range RANGECC -250 250 mV 10
CADC integral nonlinearity CCINL -1 1 LSB 11
MOS drive voltage VMOS_ON 8 10 13 V CHG, DSG, PREMOS 11
Overvoltage threshold VOV 0 4.2 6.5 V via register THR_OVSET [12:0] 12
Overvoltage recovery threshold VOVR 0 4.3 6.5 V via register THR_OVCLR [12:0] 12
Undervoltage threshold VUV 0 2.8 6.5 V via register THR_UVSET [12:0] 12
Undervoltage recovery threshold VUVR 0 2.9 6.5 V via register THR_UVCLR [12:0] 12
Discharge overcurrent threshold VOCD 10 10 200 mV via register THR_CD[4:0] 12
Discharge overcurrent delay TOCD 10 10 1280 mS via register PROT_CTRL[10:7] 12
Short-circuit threshold VSCD 20 20 400 mV via register THR_CD [9:5] 12
Short-circuit delay TSCD 0 0 448 μS via register PROT_CTRL [6:3] 12
Charge overcurrent threshold VOCC 10 10 200 mV via register THR_CD[14:10] 12
Charge overcurrent delay TOCC 10 10 1280 mS via register PROT_CTRL [2:0] 12
Low-voltage charge inhibit voltage VLV 1.638 2.5 3.25 V via register THR_LV 13
ALERT output high VALERT_OH 2.5 3.3 V ALERT external pull-up 13
ALERT output low VALERT_OL 0 0 0.6 V IOL = 1mA, ALERT external pull-up 13
ALERT input high VALERT_IH 2.5 3.6 V 13
ALERT input low VALERT_IL -0.3 0.6 V ALERT external pull-down 13
CHGD detection voltage VCHGD -950 -500 mV CHG off 13
LODD detection voltage VLODD 1 1.7 V DSG off 13
Balance duty cycle XBL 12.5 12.5 100 % PWM period 250mS 13
Balance on time TBL 0.25 1020 S via BLSW_CMD 13
ACT activation voltage VACT 2.5 3.3 5 V ACT to AGND, shutdown to standby 14
ACT shutdown voltage VSD 0 0 0.6 V ACT to AGND, standby to shutdown 14
Deep sleep wake time Twakup 0.9 1 1.1 mS DEEP = 1 sleep to standby 14
Light sleep wake time Twakup 180 200 250 μS DEEP = 0 sleep to standby 14
Input low level VIL -0.3 0 0.6 V CSN,SCLK,SDI,ALERT,PROG 14
Input high level VIH 2 3.3 4 V CSN,SCLK,SDI,ALERT,PROG 14
Output low level VOL -0.3 0 0.4 V GPIO0,GPIO1,SDO,ALERT 14
Output high level VOH 2.8 3.3 3.6 V GPIO0,GPIO1,SDO,ALERT 14
SPI clock period Tclk 500 nS 14
CSN lead time Tcs_pre 20 nS 14
CSN lag time Tcs_post 50 nS 14
Input data hold time Thold 20 nS 14

CAD (KiCad official)

  • Symbol: PB7170P48
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: pb7170p48-etched.step / pb7170p48-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pb7170p48.step / pb7170p48.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PST datasheet (32 pp, sha256 afb2082988260a54, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF