component
BQ24257RGET
Public Made by Adomby adom
Texas Instruments Battery Management, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownBQ24257RGET
Texas Instruments · Battery Management · VQFN-24(4x4)
BQ24257RGET from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CE | input | Active-low charge enable input; connecting CE to a high logic level places the battery charger in standby mode. |
| 2 | D+ | input | BC1.2 compatible D+/D- based adapter detection input that detects DCP, SDP and CDP and is connected to the USB port D+ output at power-up. |
| 3 | D- | input | BC1.2 compatible D+/D- based adapter detection input paired with D+ and connected to the USB port D- output at power-up. |
| 4 | AGND | power_in | Analog ground for the QFN package; connect to the thermal pad and the ground plane of the circuit. |
| 5 | SDA | bidirectional | I2C interface data line; connect SDA to the logic rail through a 10 kΩ resistor. |
| 6 | SCL | input | I2C interface clock input; connect SCL to the logic rail through a 10 kΩ resistor. |
| 7 | STAT | output | Open-drain status output that pulls low during charging, is high impedance when charging is complete or the charger is disabled, and sends a 256 µs fault interrupt pulse; connect through a 10 kΩ resistor or an LED to a logic rail. |
| 8 | PG | output | Open-drain power-good output (/PG) that is pulled low when a valid supply is connected to IN, where valid means between VBAT+VSLP and VOVP, and is high impedance otherwise. |
| 9 | TS | input | Battery pack NTC monitor input; connect to the center tap of a resistor divider from LDO to GND with the NTC from TS to GND, providing four thresholds for JEITA or PSE compatibility. |
| 10 | ISET | input | Charge current programming input; connect a resistor from ISET to GND to program the fast charge current. |
| 11 | BAT | bidirectional | Battery connection to the positive battery terminal; bypass BAT with at least 20 µF capacitor to GND. |
| 12 | BAT | bidirectional | Battery connection to the positive battery terminal (second BAT pin); bypass BAT with at least 20 µF capacitor to GND. |
| 13 | CSIN | input | System voltage sense and SMPS output filter connection; connect to the system output at the output bulk capacitors and bypass locally with at least 1 µF. |
| 14 | CSIN | input | System voltage sense and SMPS output filter connection (second CSIN pin); connect to the system output at the output bulk capacitors and bypass locally with at least 1 µF. |
| 15 | PGND | power_in | Power ground terminal; connect to the ground plane of the circuit and, for the QFN package, to the thermal pad of the IC. |
| 16 | PGND | power_in | Power ground terminal (second PGND pin); connect to the ground plane of the circuit and, for the QFN package, to the thermal pad of the IC. |
| 17 | SW | output | Inductor connection; connect to the switching side of the external inductor. |
| 18 | SW | output | Inductor connection (second SW pin); connect to the switching side of the external inductor. |
| 19 | IN | power_in | Input power supply connected to the external DC supply (AC adapter or USB port); bypass IN to PGND with >2 µF ceramic capacitor. |
| 20 | PMID | passive | Connection between the blocking FET and the high-side FET; connect a 1 µF capacitor from PMID to PGND as close to the PMID and PGND pins as possible. |
| 21 | BOOT | input | High-side MOSFET gate driver supply; connect a 0.033 µF ceramic capacitor with voltage rating >15 V from BOOT to SW. |
| 22 | ILIM | input | Input current limit programming input; a resistor to GND sets the limit from 0.5 A to 2 A, with ILIM shorted to GND for a 2 A default, and it has no effect on the USB input. |
| 23 | VDPM | input | Input DPM programming input; a resistor divider between IN and GND with the center tap on VDPM sets the VIN_DPM threshold with a 1.2 V regulator reference, and shorting to GND gives a default of 4.36 V. |
| 24 | LDO | power_out | LDO output regulated to 4.9 V that drives up to 50 mA; bypass LDO with a 1 µF ceramic capacitor and it is enabled when VUVLO < VIN < 19 V. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
BQ24257RGET - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
bq24257rget-etched.step/bq24257rget-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bq24257rget.step/bq24257rget.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (48 pp, sha256
ae48135cfffeee87, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).