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STM32F072VBT6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f072vbt6factory-2.0.0extractor-text
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Symbol & Footprint

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Contents

README

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STM32F072VBT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32F072VBT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5 V-tolerant I/O with alternate functions TSC_G7_IO1 and TIM3_ETR.
2 PE3 bidirectional 5 V-tolerant I/O with alternate functions TSC_G7_IO2 and TIM3_CH1.
3 PE4 bidirectional 5 V-tolerant I/O with alternate functions TSC_G7_IO3 and TIM3_CH2.
4 PE5 bidirectional 5 V-tolerant I/O with alternate functions TSC_G7_IO4 and TIM3_CH3.
5 PE6 bidirectional 5 V-tolerant I/O with alternate function TIM3_CH4 and additional functions WKUP3 and RTC_TAMP3.
6 VBAT power_in Backup power supply for RTC, 32 kHz oscillator and backup registers, 1.65 to 3.6 V.
7 PC13 bidirectional Standard 3.3 V I/O supplied through the power switch (output limited to 2 MHz, 30 pF, 3 mA sink); additional functions WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT.
8 PC14-OSC32_IN bidirectional Standard 3.3 V I/O supplied through the power switch; additional function OSC32_IN (32 kHz oscillator input).
9 PC15-OSC32_OUT bidirectional Standard 3.3 V I/O supplied through the power switch; additional function OSC32_OUT (32 kHz oscillator output).
10 PF9 bidirectional 5 V-tolerant I/O with alternate function TIM15_CH1.
11 PF10 bidirectional 5 V-tolerant I/O with alternate function TIM15_CH2.
12 PF0-OSC_IN bidirectional 5 V-tolerant I/O with alternate function CRS_SYNC and additional function OSC_IN (HSE oscillator input).
13 PF1-OSC_OUT bidirectional 5 V-tolerant I/O with additional function OSC_OUT (HSE oscillator output).
14 NRST bidirectional Device reset input / internal reset output, active low, with embedded weak pull-up.
15 PC0 bidirectional 3.3 V-tolerant I/O connected to ADC with alternate function EVENTOUT and additional function ADC_IN10.
16 PC1 bidirectional 3.3 V-tolerant I/O connected to ADC with alternate function EVENTOUT and additional function ADC_IN11.
17 PC2 bidirectional 3.3 V-tolerant I/O with SPI2_MISO, I2S2_MCK, EVENTOUT and additional function ADC_IN12.
18 PC3 bidirectional 3.3 V-tolerant I/O with SPI2_MOSI, I2S2_SD, EVENTOUT and additional function ADC_IN13.
19 PF2 bidirectional 5 V-tolerant I/O with alternate function EVENTOUT and additional function WKUP8.
20 VSSA power_in Analog ground.
21 VDDA power_in Analog power supply, from VDD to 3.6 V (minimum 2.4 V when ADC or DAC is used).
22 PF3 bidirectional 5 V-tolerant I/O with alternate function EVENTOUT.
23 PA0 bidirectional 3.3 V-tolerant I/O with USART2_CTS, TIM2_CH1_ETR, COMP1_OUT, TSC_G1_IO1, USART4_TX and additional functions RTC_TAMP2, WKUP1, ADC_IN0, COMP1_INM6.
24 PA1 bidirectional 3.3 V-tolerant I/O with USART2_RTS, TIM2_CH2, TIM15_CH1N, TSC_G1_IO2, USART4_RX, EVENTOUT and additional functions ADC_IN1, COMP1_INP.
25 PA2 bidirectional 3.3 V-tolerant I/O with USART2_TX, COMP2_OUT, TIM2_CH3, TIM15_CH1, TSC_G1_IO3 and additional functions ADC_IN2, COMP2_INM6, WKUP4.
26 PA3 bidirectional 3.3 V-tolerant I/O with USART2_RX, TIM2_CH4, TIM15_CH2, TSC_G1_IO4 and additional functions ADC_IN3, COMP2_INP.
27 VSS power_in Ground.
28 VDD power_in Digital power supply, 2.0 to 3.6 V.
29 PA4 bidirectional 3.3 V-tolerant I/O with SPI1_NSS, I2S1_WS, TIM14_CH1, TSC_G2_IO1, USART2_CK and additional functions COMP1_INM4, COMP2_INM4, ADC_IN4, DAC_OUT1.
30 PA5 bidirectional 3.3 V-tolerant I/O with SPI1_SCK, I2S1_CK, CEC, TIM2_CH1_ETR, TSC_G2_IO2 and additional functions COMP1_INM5, COMP2_INM5, ADC_IN5, DAC_OUT2.
31 PA6 bidirectional 3.3 V-tolerant I/O with SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, COMP1_OUT, TSC_G2_IO3, EVENTOUT, USART3_CTS and additional function ADC_IN6.
32 PA7 bidirectional 3.3 V-tolerant I/O with SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, COMP2_OUT, TSC_G2_IO4, EVENTOUT and additional function ADC_IN7.
33 PC4 bidirectional 3.3 V-tolerant I/O with EVENTOUT, USART3_TX and additional function ADC_IN14.
34 PC5 bidirectional 3.3 V-tolerant I/O with TSC_G3_IO1, USART3_RX and additional functions ADC_IN15, WKUP5.
35 PB0 bidirectional 3.3 V-tolerant I/O with TIM3_CH3, TIM1_CH2N, TSC_G3_IO2, EVENTOUT, USART3_CK and additional function ADC_IN8.
36 PB1 bidirectional 3.3 V-tolerant I/O with TIM3_CH4, USART3_RTS, TIM14_CH1, TIM1_CH3N, TSC_G3_IO3 and additional function ADC_IN9.
37 PB2 bidirectional 5 V-tolerant I/O with alternate function TSC_G3_IO4.
38 PE7 bidirectional 5 V-tolerant I/O with alternate function TIM1_ETR.
39 PE8 bidirectional 5 V-tolerant I/O with alternate function TIM1_CH1N.
40 PE9 bidirectional 5 V-tolerant I/O with alternate function TIM1_CH1.
41 PE10 bidirectional 5 V-tolerant I/O with alternate function TIM1_CH2N.
42 PE11 bidirectional 5 V-tolerant I/O with alternate function TIM1_CH2.
43 PE12 bidirectional 5 V-tolerant I/O with SPI1_NSS, I2S1_WS, TIM1_CH3N.
44 PE13 bidirectional 5 V-tolerant I/O with SPI1_SCK, I2S1_CK, TIM1_CH3.
45 PE14 bidirectional 5 V-tolerant I/O with SPI1_MISO, I2S1_MCK, TIM1_CH4.
46 PE15 bidirectional 5 V-tolerant I/O with SPI1_MOSI, I2S1_SD, TIM1_BKIN.
47 PB10 bidirectional 5 V-tolerant I/O with SPI2_SCK, I2C2_SCL, USART3_TX, CEC, TSC_SYNC, TIM2_CH3.
48 PB11 bidirectional 5 V-tolerant I/O with USART3_RX, TIM2_CH4, EVENTOUT, TSC_G6_IO1, I2C2_SDA.
49 VSS power_in Ground.
50 VDD power_in Digital power supply, 2.0 to 3.6 V.
51 PB12 bidirectional 5 V-tolerant I/O with TIM1_BKIN, TIM15_BKIN, SPI2_NSS, I2S2_WS, USART3_CK, TSC_G6_IO2, EVENTOUT.
52 PB13 bidirectional 5 V-tolerant I/O, FM+ capable, with SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_CTS, TIM1_CH1N, TSC_G6_IO3.
53 PB14 bidirectional 5 V-tolerant I/O, FM+ capable, with SPI2_MISO, I2S2_MCK, I2C2_SDA, USART3_RTS, TIM1_CH2N, TIM15_CH1, TSC_G6_IO4.
54 PB15 bidirectional 5 V-tolerant I/O with SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM15_CH1N, TIM15_CH2 and additional functions WKUP7, RTC_REFIN.
55 PD8 bidirectional 5 V-tolerant I/O with alternate function USART3_TX.
56 PD9 bidirectional 5 V-tolerant I/O with alternate function USART3_RX.
57 PD10 bidirectional 5 V-tolerant I/O with alternate function USART3_CK.
58 PD11 bidirectional 5 V-tolerant I/O with alternate function USART3_CTS.
59 PD12 bidirectional 5 V-tolerant I/O with USART3_RTS, TSC_G8_IO1.
60 PD13 bidirectional 5 V-tolerant I/O with alternate function TSC_G8_IO2.
61 PD14 bidirectional 5 V-tolerant I/O with alternate function TSC_G8_IO3.
62 PD15 bidirectional 5 V-tolerant I/O with TSC_G8_IO4, CRS_SYNC.
63 PC6 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with alternate function TIM3_CH1.
64 PC7 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with alternate function TIM3_CH2.
65 PC8 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with alternate function TIM3_CH3.
66 PC9 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with alternate function TIM3_CH4.
67 PA8 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with USART1_CK, TIM1_CH1, EVENTOUT, MCO, CRS_SYNC.
68 PA9 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with USART1_TX, TIM1_CH2, TIM15_BKIN, TSC_G4_IO1.
69 PA10 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with USART1_RX, TIM1_CH3, TIM17_BKIN, TSC_G4_IO2.
70 PA11 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with CAN_RX, USART1_CTS, TIM1_CH4, COMP1_OUT, TSC_G4_IO3, EVENTOUT and additional function USB_DM.
71 PA12 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with CAN_TX, USART1_RTS, TIM1_ETR, COMP2_OUT, TSC_G4_IO4, EVENTOUT and additional function USB_DP.
72 PA13 bidirectional 5 V-tolerant I/O supplied by VDDIO2, SWDIO after reset (internal pull-up active), with IR_OUT and USB_NOE.
73 PF6 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with no alternate function listed.
74 VSS power_in Ground.
75 VDDIO2 power_in Supply for the VDDIO2 I/Os, 1.65 to 3.6 V, independent of VDD/VDDA but not to be applied without a valid VDD.
76 PA14 bidirectional 5 V-tolerant I/O supplied by VDDIO2, SWCLK after reset (internal pull-down active), with USART2_TX.
77 PA15 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with SPI1_NSS, I2S1_WS, USART2_RX, USART4_RTS, TIM2_CH1_ETR, EVENTOUT.
78 PC10 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with USART3_TX, USART4_TX.
79 PC11 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with USART3_RX, USART4_RX.
80 PC12 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with USART3_CK, USART4_CK.
81 PD0 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with SPI2_NSS, I2S2_WS, CAN_RX.
82 PD1 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with SPI2_SCK, I2S2_CK, CAN_TX.
83 PD2 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with USART3_RTS, TIM3_ETR.
84 PD3 bidirectional 5 V-tolerant I/O with SPI2_MISO, I2S2_MCK, USART2_CTS.
85 PD4 bidirectional 5 V-tolerant I/O with SPI2_MOSI, I2S2_SD, USART2_RTS.
86 PD5 bidirectional 5 V-tolerant I/O with alternate function USART2_TX.
87 PD6 bidirectional 5 V-tolerant I/O with alternate function USART2_RX.
88 PD7 bidirectional 5 V-tolerant I/O with alternate function USART2_CK.
89 PB3 bidirectional 5 V-tolerant I/O with SPI1_SCK, I2S1_CK, TIM2_CH2, TSC_G5_IO1, EVENTOUT.
90 PB4 bidirectional 5 V-tolerant I/O with SPI1_MISO, I2S1_MCK, TIM17_BKIN, TIM3_CH1, TSC_G5_IO2, EVENTOUT.
91 PB5 bidirectional 5 V-tolerant I/O with SPI1_MOSI, I2S1_SD, I2C1_SMBA, TIM16_BKIN, TIM3_CH2 and additional function WKUP6.
92 PB6 bidirectional 5 V-tolerant I/O, FM+ capable, with I2C1_SCL, USART1_TX, TIM16_CH1N, TSC_G5_IO3.
93 PB7 bidirectional 5 V-tolerant I/O, FM+ capable, with I2C1_SDA, USART1_RX, USART4_CTS, TIM17_CH1N, TSC_G5_IO4.
94 BOOT0 input Dedicated boot memory selection input.
95 PB8 bidirectional 5 V-tolerant I/O, FM+ capable, with I2C1_SCL, CEC, TIM16_CH1, TSC_SYNC, CAN_RX.
96 PB9 bidirectional 5 V-tolerant I/O, FM+ capable, with SPI2_NSS, I2S2_WS, I2C1_SDA, IR_OUT, TIM17_CH1, EVENTOUT, CAN_TX.
97 PE0 bidirectional 5 V-tolerant I/O with EVENTOUT, TIM16_CH1.
98 PE1 bidirectional 5 V-tolerant I/O with EVENTOUT, TIM17_CH1.
99 VSS power_in Ground.
100 VDD power_in Digital power supply, 2.0 to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: STM32F072VBT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32f072vbt6-etched.step / stm32f072vbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f072vbt6.step / stm32f072vbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (128 pp, sha256 b01391f094699aeb, retrieved 2026-10-01, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF