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Contents

README

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TPS7A8033DRBR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SON-8-EP(3x3)

TPS7A8033DRBR from Texas Instruments, in a SON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Regulator output; a 4.7-μF or larger capacitor of any type is required for stability.
2 OUT power_out Regulator output; a 4.7-μF or larger capacitor of any type is required for stability.
3 FB/SNS input For the fixed-output version this pin is the output voltage sense (SNS) input, which should be connected close to the load to minimize trace resistive drop.
4 GND power_in Ground reference for the regulator.
5 EN input Driving EN high turns the regulator on and driving it low puts it into shutdown; EN must not be left floating and can be connected to IN if not used.
6 NR passive Connect an external capacitor between NR and ground to reduce output noise to very low levels and to slow the VOUT ramp (RC soft-start).
7 IN power_in Unregulated input supply to the regulator.
8 IN power_in Unregulated input supply to the regulator.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SON-8-EP(3x3)
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Internal reference VNR 1.23 1.243 1.26 V Fixed VOUT ≥ 1.8 V 6
Output voltage VOUT 1.2 5 V Fixed versions only 6
Output accuracy -2 2 % VOUT + 0.5 V ≤ VIN ≤ 6 V, VIN ≥ 2.5 V, 100 mA ≤ IOUT ≤ 500 mA, 0°C ≤ TJ ≤ 85°C 6
Output accuracy -3 3 % VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V, 100 mA ≤ IOUT ≤ 1 A 6
Line regulation ΔVOUT/ΔVIN 150 μV/V VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V, IOUT = 100 mA 6
Load regulation ΔVOUT/ΔIOUT 2 μV/mA 100 mA ≤ IOUT ≤ 1 A 6
Dropout voltage VDO 250 mV VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V, IOUT = 500 mA, VFB = GND or VSNS = GND 6
Dropout voltage VDO 350 mV VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.5 V, IOUT = 750 mA, VFB = GND or VSNS = GND 6
Dropout voltage VDO 500 mV VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.5 V, IOUT = 1 A, VFB = GND or VSNS = GND 6
Output current limit (fixed) ICL 1100 2000 mA VOUT = 0.85 × VOUT(NOM), VIN ≥ 3.3 V 6
Ground pin current IGND 120 μA IOUT = 1 mA, fixed versions only 6
Ground pin current IGND 350 μA IOUT = 1 A 6
Shutdown current (IGND) ISHDN 2 μA VEN ≤ 0.4 V, VIN ≥ 2.2 V, RL = 1 kΩ, 0°C ≤ TJ ≤ 85°C 6
Enable pin current, enabled IEN(HI) 1 μA VIN = VEN = 6.5 V 6
Enable high (enabled) VEN(HI) 1.2 V 2.2 V ≤ VIN ≤ 3.6 V, RL = 1 kΩ 6
Enable high (enabled) VEN(HI) 1.35 V 3.6 V < VIN ≤ 6.5 V, RL = 1 kΩ 6
Enable low (shutdown) VEN(LO) 0 0.4 V RL = 1 kΩ 6
Undervoltage lockout UVLO 1.86 2 2.1 V VIN rising, RL = 1 kΩ 6
Input voltage absolute maximum VIN -0.3 7 V 5
FB, NR voltage absolute maximum -0.3 3.6 V 5
OUT voltage absolute maximum VOUT -0.3 7 V 5
Operating virtual junction temperature TJ -55 150 °C 5
Operating free-air temperature TA -40 125 °C 5
Storage temperature Tstg -55 150 °C 5
Input voltage VIN 2.2 6.5 V 5
Output current IOUT 0 1 A 5
Operating junction temperature TJ -40 125 °C 5
Operating free air temperature TA -40 125 °C 5
Thermal shutdown temperature, shutdown 160 °C Shutdown, temperature increasing 6
Thermal shutdown temperature, reset 140 °C Reset, temperature decreasing 6
Junction-to-ambient thermal resistance RθJA 47.8 °C/W DRB (VSON) package 5
Junction-to-case (top) thermal resistance RθJC(top) 53.9 °C/W DRB (VSON) package 5
Junction-to-board thermal resistance RθJB 23.4 °C/W DRB (VSON) package 5
Junction-to-top characterization parameter ψJT 1 °C/W DRB (VSON) package 5
Junction-to-board characterization parameter ψJB 23.5 °C/W DRB (VSON) package 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 7.4 °C/W DRB (VSON) package 5

CAD (KiCad official)

  • Symbol: TPS7A8033DRBR
  • Footprint: Package_SON:WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm
  • 3D model: SON-8-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps7a8033drbr-etched.step / tps7a8033drbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7a8033drbr.step / tps7a8033drbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 0938ecd05ac1b382, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF