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MSP430G2203IRHB32R
Public Made by Adomby adom
Texas Instruments Microcontroller Units (MCUs/MPUs/SOCs), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430G2203IRHB32R
Texas Instruments · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-32-EP(5x5)
MSP430G2203IRHB32R from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1 | bidirectional | General-purpose digital I/O with Timer0_A CCI0A capture and Out0 compare, USCI_A0 UART receive or SPI slave out/master in, and BSL transmit; the A1 ADC10 input is MSP430G2x33 only. |
| 2 | P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2 | bidirectional | General-purpose digital I/O with Timer0_A CCI1A capture and Out1 compare, and USCI_A0 UART transmit or SPI slave in/master out; the A2 ADC10 input is MSP430G2x33 only. |
| 3 | P1.3/ADC10CLK/A3/VREF-/VEREF- | bidirectional | General-purpose digital I/O; its ADC10 clock, A3 input and VREF-/VEREF- functions are available on MSP430G2x33 devices only. |
| 4 | P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/TCK | bidirectional | General-purpose digital I/O with SMCLK output, USCI_B0 slave transmit enable, USCI_A0 clock, and JTAG TCK test clock input for device programming and test; the ADC10 functions are MSP430G2x33 only. |
| 5 | P1.5/TA0.0/UCB0CLK/UCA0STE/A5/TMS | bidirectional | General-purpose digital I/O with Timer0_A Out0 compare, USCI clock and slave transmit enable, BSL receive, and JTAG TMS test mode select input; the A5 ADC10 input is MSP430G2x33 only. |
| 6 | P3.1/TA1.0 | bidirectional | General-purpose digital I/O with Timer1_A Out0 compare output. |
| 7 | P3.0/TA0.2 | bidirectional | General-purpose digital I/O with Timer0_A CCI2A capture and Out2 compare output. |
| 8 | NC | unconnected | Not connected. |
| 9 | P2.0/TA1.0 | bidirectional | General-purpose digital I/O with Timer1_A CCI0A capture and Out0 compare output. |
| 10 | P2.1/TA1.1 | bidirectional | General-purpose digital I/O with Timer1_A CCI1A capture and Out1 compare output. |
| 11 | P2.2/TA1.1 | bidirectional | General-purpose digital I/O with Timer1_A CCI1B capture and Out1 compare output. |
| 12 | P3.2/TA1.1 | bidirectional | General-purpose digital I/O with Timer1_A Out1 compare output. |
| 13 | P3.3/TA1.2 | bidirectional | General-purpose digital I/O with Timer1_A Out2 compare output. |
| 14 | P3.4/TA0.0 | bidirectional | General-purpose digital I/O with Timer0_A Out0 compare output. |
| 15 | P2.3/TA1.0 | bidirectional | General-purpose digital I/O with Timer1_A CCI0B capture and Out0 compare output. |
| 16 | P2.4/TA1.2 | bidirectional | General-purpose digital I/O with Timer1_A CCI2A capture and Out2 compare output. |
| 17 | P2.5/TA1.2 | bidirectional | General-purpose digital I/O with Timer1_A CCI2B capture and Out2 compare output. |
| 18 | P3.5/TA0.1 | bidirectional | General-purpose digital I/O with Timer0_A Out1 compare output. |
| 19 | P3.6/TA0.2 | bidirectional | General-purpose digital I/O with Timer0_A Out2 compare output. |
| 20 | P3.7/TA1CLK | bidirectional | General-purpose digital I/O with Timer1_A TACLK clock signal input. |
| 21 | P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/TDI/TCLK | bidirectional | General-purpose digital I/O with Timer0_A Out1 compare, USCI_B0 SPI slave out/master in or I2C SCL, and JTAG TDI/TCLK input; the A6 ADC10 input is MSP430G2x33 only. |
| 22 | P1.7/UCB0SIMO/UCB0SDA/A7/TDO/TDI | bidirectional | General-purpose digital I/O with USCI_B0 SPI slave in/master out or I2C SDA, and JTAG TDO/TDI test data output or input; the A7 ADC10 input is MSP430G2x33 only. |
| 23 | RST/NMI/SBWTDIO | input | Reset input, nonmaskable interrupt input, and Spy-Bi-Wire test data input/output during programming and test. |
| 24 | TEST/SBWTCK | input | Selects test mode for the JTAG pins on Port 1 and carries the device protection fuse connection; also Spy-Bi-Wire test clock input during programming and test. |
| 25 | XOUT/P2.7 | bidirectional | Output terminal of the crystal oscillator or general-purpose digital I/O; if used as input, excess current flows until P2SEL.7 is cleared. |
| 26 | XIN/P2.6/TA0.1 | bidirectional | Input terminal of the crystal oscillator or general-purpose digital I/O with Timer0_A Out1 compare output. |
| 27 | AVSS | power_in | Analog ground reference shown on the 32-pin device figure; Table 2 groups pins 27 and 28 together as DVSS. |
| 28 | DVSS | power_in | Digital ground reference. |
| 29 | AVCC | power_in | Analog supply voltage (RHB package only). |
| 30 | DVCC | power_in | Digital supply voltage. |
| 31 | P1.0/TA0CLK/ACLK/A0 | bidirectional | General-purpose digital I/O with Timer0_A TACLK input and ACLK signal output; the A0 ADC10 input is MSP430G2x33 only. |
| 32 | NC | unconnected | Not connected. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
MSP430G2203IRHB32R - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
msp430g2203irhb32r-etched.step/msp430g2203irhb32r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430g2203irhb32r.step/msp430g2203irhb32r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (80 pp, sha256
f80b48af390c6f87, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).