C8051F582-IM from SILICON LABS, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P0.1	bidirectional	Port 0.1 is a digital I/O or analog input pin, and is also the CNVSTR pin used when the ADC is set to use the external conversion start signal.
2	VIO	power_in	Port I/O supply voltage that must be connected and should be tied to the voltage source of the interface logic in multi-voltage systems.
3	VREGIN	power_in	Voltage regulator input for the on-chip voltage regulator.
4	VDD	power_in	Digital supply voltage that must be connected; the device is specified for 1.8 V to 5.25 V operation.
5	VDDA	power_in	Analog supply voltage that must be connected.
6	GND	power_in	Digital ground that must be connected.
7	GNDA	power_in	Analog ground that must be connected.
8	P0.0	bidirectional	Port 0.0 is a digital I/O or analog input pin, and is also the VREF pin; if VDD is selected as the reference and the ADC is enabled, it cannot be used in open-drain mode.
9	P3.0/C2D	bidirectional	Port 3.0 is a digital I/O or analog input pin that is also the bi-directional data signal for the C2 Debug Interface.
10	RST/C2CK	bidirectional	Device reset pin that is an open-drain output of the internal POR or VDD Monitor, which an external source can drive low to initiate a system reset; it also carries the C2 Debug Interface clock signal.
11	P2.7	bidirectional	Port 2.7 is a digital I/O or analog input pin.
12	P2.6	bidirectional	Port 2.6 is a digital I/O or analog input pin.
13	P2.5	bidirectional	Port 2.5 is a digital I/O or analog input pin.
14	P2.4	bidirectional	Port 2.4 is a digital I/O or analog input pin.
15	P2.3	bidirectional	Port 2.3 is a digital I/O or analog input pin.
16	P2.2	bidirectional	Port 2.2 is a digital I/O or analog input pin.
17	P2.1	bidirectional	Port 2.1 is a digital I/O or analog input pin.
18	P2.0	bidirectional	Port 2.0 is a digital I/O or analog input pin.
19	P1.7	bidirectional	Port 1.7 is a digital I/O or analog input pin that can be assigned to crossbar functions or used as GPIO.
20	P1.6	bidirectional	Port 1.6 is a digital I/O or analog input pin that can be assigned to crossbar functions or used as GPIO.
21	P1.5	bidirectional	Port 1.5 is a digital I/O or analog input pin that can be assigned to crossbar functions or used as GPIO.
22	P1.4	bidirectional	Port 1.4 is a digital I/O or analog input pin that can be assigned to crossbar functions or used as GPIO.
23	P1.3	bidirectional	Port 1.3 is a digital I/O or analog input pin that can be assigned to crossbar functions or used as GPIO.
24	P1.2	bidirectional	Port 1.2 is a digital I/O or analog input pin that can be assigned to crossbar functions or used as GPIO.
25	P1.1	bidirectional	Port 1.1 is a digital I/O or analog input pin that can be assigned to crossbar functions or used as GPIO.
26	P1.0	bidirectional	Port 1.0 is a digital I/O or analog input pin that can be assigned to crossbar functions or used as GPIO.
27	P0.7	bidirectional	Port 0.7 is a digital I/O or analog input pin, and is the fixed CAN0 RX pin assignment.
28	P0.6	bidirectional	Port 0.6 is a digital I/O or analog input pin, and is the fixed CAN0 TX pin assignment.
29	P0.5	bidirectional	Port 0.5 is a digital I/O or analog input pin, and is the fixed UART0 RX pin assignment.
30	P0.4	bidirectional	Port 0.4 is a digital I/O or analog input pin, and is the fixed UART0 TX pin assignment.
31	P0.3	bidirectional	Port 0.3 is a digital I/O or analog input pin, and serves as XTAL2 when the external oscillator circuit is enabled.
32	P0.2	bidirectional	Port 0.2 is a digital I/O or analog input pin, and serves as XTAL1 when the external oscillator circuit is enabled.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	SILICON LABS
Package	QFN-32-EP(5x5)
Category	Embedded Processors & Controllers
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Ambient Temperature under Bias		-55		135	°C		41
Storage Temperature		-65		150	°C		41
Voltage on VREGIN with Respect to GND	VREGIN	-0.3		5.5	V		41
Voltage on VDD with Respect to GND	VDD	-0.3		2.8	V		41
Voltage on VDDA with Respect to GND	VDDA	-0.3		2.8	V		41
Voltage on VIO with Respect to GND	VIO	-0.3		5.5	V		41
Maximum Total Current through VREGIN or GND				500	mA		41
Maximum Output Current Sunk by RST or any Port Pin				100	mA		41
Maximum Output Current Sourced by any Port Pin				100	mA		41
Supply Input Voltage (VREGIN)	VREGIN	1.8		5.25	V		42
Specified Operating Temperature Range		-40		125	°C		42
Digital Supply Voltage (VDD)	VDD			2.75	V	System Clock < 25 MHz	42
Digital Supply Voltage (VDD)	VDD	2.75			V	System Clock > 25 MHz	42
Analog Supply Voltage (VDDA)	VDDA			2.75	V	System Clock < 25 MHz	42
Analog Supply Voltage (VDDA)	VDDA	2.75			V	System Clock > 25 MHz	42
Port I/O Supply Voltage (VIO)	VIO	1.8		5.25	V	Normal Operation	42
SYSCLK (System Clock)	SYSCLK	0		50	MHz		42
SYSCLK High Time	TSYSH	9			ns		42
SYSCLK Low Time	TSYSL	9			ns		42
Digital Supply Current, CPU Active	IDD		8.5	11	mA	VDD = 2.1 V, F = 25 MHz	42
Digital Supply Current, CPU Active	IDD		15	21	mA	VDD = 2.1 V, F = 50 MHz	42
Digital Supply Current, CPU Active	IDD		12	21	mA	VDD = 2.6 V, F = 25 MHz	43
Digital Supply Current, CPU Active	IDD		21	33	mA	VDD = 2.6 V, F = 50 MHz	43
Digital Supply Current, CPU Inactive (Idle Mode)	IDD		5.8	8	mA	VDD = 2.1 V, F = 25 MHz	44
Digital Supply Current, CPU Inactive (Idle Mode)	IDD		11	16	mA	VDD = 2.1 V, F = 50 MHz	44
Digital Supply Current, CPU Inactive (Idle Mode)	IDD		7.3	15	mA	VDD = 2.6 V, F = 25 MHz	44
Digital Supply Current, CPU Inactive (Idle Mode)	IDD		15	25	mA	VDD = 2.6 V, F = 50 MHz	44
RST Output Low Voltage				40	mV	VIO = 5.0 V; IOL = 70 µA	47
RST Input Pullup Current			45	115	µA	RST = 0.0 V	47
VDD POR Threshold (VRST-LOW)	VRST-LOW	1.65	1.75	1.8	V		47
VDD POR Threshold (VRST-HIGH)	VRST-HIGH	2.25	2.3	2.45	V		47
VDD Ramp Time for Power On				1	ms	VDD Ramp 0-1.8 V	47
Missing Clock Detector Timeout		200	390	600	µs	VDD = 2.1 V	47
Missing Clock Detector Timeout		200	280	600	µs	VDD = 2.5 V	47
Reset Time Delay			130	160	µs	Delay between release of any reset source and code execution at location 0x0000	47
Minimum RST Low Time to Generate a System Reset		6			µs		47
VDD Monitor Turn-on Time			60	100	µs		47
VDD Monitor Settling Time				2	µs	VDMLVL changes state or VDMCAL registers are written	47
VDD Monitor Supply Current			1	2	µA		47
Endurance		20	150		k Erase/Write		48
Flash Retention		10			years	85 °C	48
Erase Cycle Time		28	30	45	ms	25 MHz System Clock	48
Write Cycle Time		79	84	125	µs	25 MHz System Clock	48
Temperature during Programming Operations		0		125	°C	-I Devices	48
Internal Oscillator Frequency (24 MHz) tolerance		-0.5		0.5	%	IFCN = 111b; VDD > VREGMIN	48
Internal Oscillator Frequency (24 MHz) tolerance		-1		1	%	IFCN = 111b; VDD < VREGMIN	48
Oscillator Supply Current (from VDD)			880	1300	µA	Internal Oscillator On, OSCICN[7:6] = 11b	48
Output Voltage (VDD)	VDD	2	2.1	2.25	V	2.1 V operation (REG0MD = 0)	49
Output Voltage (VDD)	VDD	2.5	2.6	2.75	V	2.6 V operation (REG0MD = 1)	49
Voltage Regulator Bias Current			1	9	µA		49
Dropout Indicator Detection Threshold		-0.21		-0.02	V	With respect to VDD	49
Output Low Voltage				50	mV	VIO = 1.8 V; IOL = 70 µA	46
Output Low Voltage				750	mV	VIO = 1.8 V; IOL = 8.5 mA	46
Output Low Voltage				45	mV	VIO = 2.7 V; IOL = 70 µA	46
Output Low Voltage				550	mV	VIO = 2.7 V; IOL = 8.5 mA	46
Output Low Voltage				40	mV	VIO = 5.25 V; IOL = 70 µA	46
Output Low Voltage				400	mV	VIO = 5.25 V; IOL = 8.5 mA	46
Integral Nonlinearity		-3	0.5	3	LSB		50
Offset Error		-10	-1.6	10	LSB		50
Full Scale Error		-20	-4.2	20	LSB		50

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	PC		4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body	31

CAD (KiCad official)

Symbol: C8051F582-IM
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: c8051f582-im-etched.step / c8051f582-im-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f582-im.step / c8051f582-im.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: SILICON LABS datasheet (361 pp, sha256 43992a079d5dbe76, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

C8051F582-IM

Verified C8051F582-IM

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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