component
AT32F421K8T7
Public Made by Adomby adom
ARTERY Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAT32F421K8T7
ARTERY · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)
AT32F421K8T7 from ARTERY, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Digital supply for I/O pins, ERTC, LSE, backup registers and the internal regulator, specified at 2.4 V to 3.6 V. |
| 2 | PF0 / OSC_IN | bidirectional | Standard-level (TC, not 5 V tolerant) GPIO that doubles as the HSE oscillator input OSC_IN (4-25 MHz crystal/resonator) and I2C1_SDA. |
| 3 | PF1 / OSC_OUT | bidirectional | Standard-level (TC, not 5 V tolerant) GPIO that doubles as the HSE oscillator output OSC_OUT and I2C1_SCL. |
| 4 | NRST | bidirectional | Active-low device reset input and internal reset output with a built-in weak pull-up (RPU typically 40 kΩ, 30-50 kΩ range). |
| 5 | VDDA / VREF+ | power_in | Analog supply for the ADC and comparator (2.4 V to 3.6 V), which must be connected to VDD, and also the positive ADC reference VREF+. |
| 6 | PA0 | bidirectional | 5 V tolerant (FTa) GPIO with ADC_IN0, COMP_INP2/COMP_INM6, WKUP1, TMR1_ETR, USART2_CTS, I2C2_SCL and COMP_OUT functions; in analog mode the input must stay below VDD + 0.3 V. |
| 7 | PA1 | bidirectional | 5 V tolerant (FTa) GPIO with ADC_IN1, COMP_INP1, TMR15_CH1N, USART2_RTS, I2C2_SDA and EVENTOUT functions; in analog mode the input must stay below VDD + 0.3 V. |
| 8 | PA2 | bidirectional | 5 V tolerant (FTa) GPIO with ADC_IN2, COMP2_INM7, TMR15_CH1 and USART2_TX functions; in analog mode the input must stay below VDD + 0.3 V. |
| 9 | PA3 | bidirectional | 5 V tolerant (FTa) GPIO with ADC_IN3, TMR15_CH2, USART2_RX and I2S2_MCK functions; in analog mode the input must stay below VDD + 0.3 V. |
| 10 | PA4 | bidirectional | 5 V tolerant (FTa) GPIO with ADC_IN4, COMP_INM4, TMR14_CH1, USART2_CK, SPI1_NSS and I2S1_WS functions; in analog mode the input must stay below VDD + 0.3 V. |
| 11 | PA5 | bidirectional | 5 V tolerant (FTa) GPIO with ADC_IN5, COMP_INP0, COMP_INM5, SPI1_SCK and I2S1_CK functions; in analog mode the input must stay below VDD + 0.3 V. |
| 12 | PA6 | bidirectional | 5 V tolerant (FTa) GPIO with ADC_IN6, TMR1_BKIN, TMR3_CH1, TMR16_CH1, SPI1_MISO, I2S1_MCK, I2S2_MCK, COMP_OUT and EVENTOUT functions; in analog mode the input must stay below VDD + 0.3 V. |
| 13 | PA7 | bidirectional | 5 V tolerant (FTa) GPIO with ADC_IN7, TMR1_CH1N, TMR3_CH2, TMR14_CH1, TMR17_CH1, SPI1_MOSI, I2S1_SD and EVENTOUT functions; in analog mode the input must stay below VDD + 0.3 V. |
| 14 | PB0 | bidirectional | 5 V tolerant (FTa) GPIO with ADC_IN8, TMR1_CH2N, TMR3_CH3, USART2_RX, I2S1_MCK and EVENTOUT functions; in analog mode the input must stay below VDD + 0.3 V. |
| 15 | PB1 | bidirectional | 5 V tolerant (FTa) GPIO with ADC_IN9, TMR1_CH3N, TMR3_CH4, TMR14_CH1, SPI2_SCK and I2S2_CK functions; in analog mode the input must stay below VDD + 0.3 V. |
| 16 | VSS | power_in | Digital ground. |
| 17 | VDD | power_in | Digital supply for I/O pins, ERTC, LSE, backup registers and the internal regulator, specified at 2.4 V to 3.6 V. |
| 18 | PA8 | bidirectional | 5 V tolerant (FT) GPIO with TMR1_CH1, USART1_CK, UART2_TX, I2C2_SCL, CLKOUT and EVENTOUT functions. |
| 19 | PA9 | bidirectional | 5 V tolerant (FT) GPIO with TMR1_CH2, TMR15_BKIN, USART1_TX, I2C1_SCL, I2C2_SMBA and CLKOUT functions. |
| 20 | PA10 | bidirectional | 5 V tolerant (FT) GPIO with TMR1_CH3, TMR17_BKIN, USART1_RX and I2C1_SDA functions. |
| 21 | PA11 | bidirectional | 5 V tolerant (FT) GPIO with TMR1_CH4, USART1_CTS, I2C1_SMBA, I2C2_SCL, COMP_OUT and EVENTOUT functions. |
| 22 | PA12 | bidirectional | 5 V tolerant (FT) GPIO with TMR1_ETR, USART1_RTS, I2C2_SDA and EVENTOUT functions. |
| 23 | PA13 | bidirectional | 5 V tolerant (FT) GPIO that is configured as the SWDIO serial-wire debug data pin after reset, with its internal pull-up enabled; also IR_OUT, SPI2_MISO and I2S2_MCK. |
| 24 | PA14 | bidirectional | 5 V tolerant (FT) GPIO that is configured as the SWCLK serial-wire debug clock pin after reset, with its internal pull-down enabled; also USART2_TX, SPI2_MOSI and I2S2_SD. |
| 25 | PA15 | bidirectional | 5 V tolerant (FT) GPIO with USART2_RX, SPI1_NSS, I2S1_WS, SPI2_NSS, I2S2_WS and EVENTOUT functions. |
| 26 | PB3 | bidirectional | 5 V tolerant (FT) GPIO with SPI1_SCK, I2S1_CK, SPI2_SCK, I2S2_CK and EVENTOUT functions. |
| 27 | PB4 | bidirectional | 5 V tolerant (FT) GPIO with TMR3_CH1, TMR17_BKIN, SPI1_MISO, I2S1_MCK, SPI2_MISO, I2S2_MCK, I2C2_SDA and EVENTOUT functions. |
| 28 | PB5 | bidirectional | 5 V tolerant (FT) GPIO with WKUP6, TMR3_CH2, TMR16_BKIN, SPI1_MOSI, I2S1_SD, SPI2_MOSI, I2S2_SD and I2C1_SMBA functions. |
| 29 | PB6 | bidirectional | 5 V tolerant (FT) GPIO with TMR16_CH1N, USART1_TX, I2S1_MCK and I2C1_SCL functions. |
| 30 | PB7 | bidirectional | 5 V tolerant (FT) GPIO with TMR17_CH1N, USART1_RX and I2C1_SDA functions. |
| 31 | BOOT0 | input | Boot mode selection input (with nBOOT1 user option bit) sampled at startup, with a built-in weak pull-down that cannot be disabled. |
| 32 | VSS | power_in | Digital ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ARTERY |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (VDD and I/O) | 2.4 | 3.6 | V | Power supply and I/O pins, feature summary | 1 | ||
| Operating temperature range | -40 | 105 | °C | Temperature range | 1 | ||
| 48 MHz RC oscillator accuracy (factory calibrated) | -1 | 1 | % | TA = 25 °C | 1 | ||
| 48 MHz RC oscillator accuracy (factory calibrated) | -2 | 2 | % | TA = -40 °C to +105 °C | 1 | ||
| External crystal oscillator frequency | 4 | 25 | MHz | HSE crystal oscillator, feature summary | 1 | ||
| CPU operating frequency | fAHB | 120 | MHz | Maximum, with memory protection unit (MPU) | 1 |
CAD (KiCad official)
- Symbol:
AT32F421K8T7 - Footprint:
Package_QFP:LQFP-32_7x7mm_P0.8mm - 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files:
at32f421k8t7-etched.step/at32f421k8t7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at32f421k8t7.step/at32f421k8t7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ARTERY datasheet (80 pp, sha256
13db109fb9f3fe38, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).