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74AHC573PW

Public Made by Adom

by adom

NXP Semicon Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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74AHC573PW

NXP Semicon · Latches · TSSOP-20

74AHC573PW from NXP Semicon, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output enable input (active LOW); a HIGH forces Qn outputs to the high-impedance OFF-state without affecting the latch states.
2 D0 input Data input D0 of the octal D-type transparent latch, entering the latch when LE is HIGH.
3 D1 input Data input D1 of the octal D-type transparent latch, entering the latch when LE is HIGH.
4 D2 input Data input D2 of the octal D-type transparent latch, entering the latch when LE is HIGH.
5 D3 input Data input D3 of the octal D-type transparent latch, entering the latch when LE is HIGH.
6 D4 input Data input D4 of the octal D-type transparent latch, entering the latch when LE is HIGH.
7 D5 input Data input D5 of the octal D-type transparent latch, entering the latch when LE is HIGH.
8 D6 input Data input D6 of the octal D-type transparent latch, entering the latch when LE is HIGH.
9 D7 input Data input D7 of the octal D-type transparent latch, entering the latch when LE is HIGH.
10 GND power_in Ground (0 V) reference for all device voltages.
11 LE input Latch enable input (active HIGH); latches are transparent while HIGH and store data on the HIGH-to-LOW transition.
12 Q7 tri_state 3-state data output Q7 of the latch, high-impedance when OE is HIGH.
13 Q6 tri_state 3-state data output Q6 of the latch, high-impedance when OE is HIGH.
14 Q5 tri_state 3-state data output Q5 of the latch, high-impedance when OE is HIGH.
15 Q4 tri_state 3-state data output Q4 of the latch, high-impedance when OE is HIGH.
16 Q3 tri_state 3-state data output Q3 of the latch, high-impedance when OE is HIGH.
17 Q2 tri_state 3-state data output Q2 of the latch, high-impedance when OE is HIGH.
18 Q1 tri_state 3-state data output Q1 of the latch, high-impedance when OE is HIGH.
19 Q0 tri_state 3-state data output Q0 of the latch, high-impedance when OE is HIGH.
20 VCC power_in Supply voltage; recommended range is 2.0 V to 5.5 V for 74AHC573 and 4.5 V to 5.5 V for 74AHCT573.

Key specifications

Parameter Value
Manufacturer NXP Semicon
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 5
Input voltage VI -0.5 7 V 5
Input clamping current IIK -20 mA VI < -0.5 V 5
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 5
Output current IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V) 5
Supply current ICC 75 mA 5
Ground current IGND -75 mA 5
Storage temperature Tstg -65 150 °C 5
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 5
Supply voltage VCC 2 5 5.5 V 5
Input voltage VI 0 5.5 V 5
Output voltage VO 0 V 5
Ambient temperature Tamb -40 25 125 °C 5
Input transition rise and fall rate Δt/ΔV 100 ns/V VCC = 3.3 V ± 0.3 V 5
Input transition rise and fall rate Δt/ΔV 20 ns/V VCC = 5.0 V ± 0.5 V 5
HIGH-level input voltage VIH 1.5 V VCC = 2.0 V 6
HIGH-level input voltage VIH 2.1 V VCC = 3.0 V 6
HIGH-level input voltage VIH 3.85 V VCC = 5.5 V 6
LOW-level input voltage VIL 0.5 V VCC = 2.0 V 6
LOW-level input voltage VIL 0.9 V VCC = 3.0 V 6
LOW-level input voltage VIL 1.65 V VCC = 5.5 V 6
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V 6
HIGH-level output voltage VOH 2.9 3 V VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V 6
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V 6
HIGH-level output voltage VOH 2.58 V VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V 6
HIGH-level output voltage VOH 3.94 V VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V 6
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V 6
LOW-level output voltage VOL 0.36 V VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V 6
OFF-state output current IOZ -0.25 0.25 μA VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V 6
Input leakage current II 0.1 0.1 μA VI = VCC or GND; VCC = 0 V to 5.5 V 6
Supply current ICC 4 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V 6
Input capacitance CI 3 10 pF VI = VCC or GND 6
Propagation delay Dn to Qn tpd 5.5 11 ns Dn to Qn; see Fig. 5; VCC = 3.0 V to 3.6 V; CL = 15 pF 8
Propagation delay Dn to Qn tpd 7.8 14.5 ns Dn to Qn; see Fig. 5; VCC = 3.0 V to 3.6 V; CL = 50 pF 8
Propagation delay Dn to Qn tpd 3.9 6.8 ns Dn to Qn; see Fig. 5; VCC = 4.5 V to 5.5 V; CL = 15 pF 8
Propagation delay Dn to Qn tpd 5.5 8.8 ns Dn to Qn; see Fig. 5; VCC = 4.5 V to 5.5 V; CL = 50 pF 8
Propagation delay LE to Qn tpd 5.8 11.9 ns LE to Qn; see Fig. 6; VCC = 3.0 V to 3.6 V; CL = 15 pF 8
Propagation delay LE to Qn tpd 8.3 15.4 ns LE to Qn; see Fig. 6; VCC = 3.0 V to 3.6 V; CL = 50 pF 8
Propagation delay LE to Qn tpd 4.2 7.7 ns LE to Qn; see Fig. 6; VCC = 4.5 V to 5.5 V; CL = 15 pF 8
Propagation delay LE to Qn tpd 5.9 9.7 ns LE to Qn; see Fig. 6; VCC = 4.5 V to 5.5 V; CL = 50 pF 8
Enable time OE to Qn ten 5.8 11.5 ns OE to Qn; see Fig. 7; VCC = 3.0 V to 3.6 V; CL = 15 pF 8
Enable time OE to Qn ten 8.3 15 ns OE to Qn; see Fig. 7; VCC = 3.0 V to 3.6 V; CL = 50 pF 8
Enable time OE to Qn ten 4.4 7.7 ns OE to Qn; see Fig. 7; VCC = 4.5 V to 5.5 V; CL = 15 pF 8
Enable time OE to Qn ten 6.3 9.7 ns OE to Qn; see Fig. 7; VCC = 4.5 V to 5.5 V; CL = 50 pF 8
Disable time OE to Qn tdis 6.8 11 ns OE to Qn; see Fig. 7; VCC = 3.0 V to 3.6 V; CL = 15 pF 8
Disable time OE to Qn tdis 9.7 14.5 ns OE to Qn; see Fig. 7; VCC = 3.0 V to 3.6 V; CL = 50 pF 8
Disable time OE to Qn tdis 4.6 7.7 ns OE to Qn; see Fig. 7; VCC = 4.5 V to 5.5 V; CL = 15 pF 8
Disable time OE to Qn tdis 7.4 9.7 ns OE to Qn; see Fig. 7; VCC = 4.5 V to 5.5 V; CL = 50 pF 8
Pulse width LE HIGH tW 5 ns LE HIGH; see Fig. 6; VCC = 3.0 V to 3.6 V 8
Set-up time Dn to LE tsu 3.5 ns Dn to LE; see Fig. 8; VCC = 3.0 V to 3.6 V 8
Hold time Dn to LE th 1.5 ns Dn to LE; see Fig. 8; VCC = 3.0 V to 3.6 V 8

CAD (KiCad official)

  • Symbol: 74AHC573PW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74ahc573pw-etched.step / 74ahc573pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74ahc573pw.step / 74ahc573pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NXP Semicon datasheet (17 pp, sha256 70a39eb3d8b5f2b1, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF