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TPS55332QPWPRQ1

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Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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TPS55332QPWPRQ1

Texas Instruments · DC-DC Converters · HTSSOP-20-EP

TPS55332QPWPRQ1 from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Not internally connected; the datasheet says to connect this pin to ground.
2 NC unconnected Not internally connected; the datasheet says to connect this pin to ground.
3 SYNC input External synchronization clock input with a 62-kΩ (typ) pull-down resistor.
4 GND power_in Connect to ground.
5 EN input Enable input for on/off control of the regulator, high-voltage tolerant.
6 RT passive Resistor connection that programs the internal oscillator frequency.
7 Rslew passive Connection for the internal switch programmable slew-rate control.
8 RST output Reset output, open drain and active low.
9 Cdly passive Reset delay timer, programmed by an external capacitor.
10 GND power_in Analog ground (DVSS and substrate reference); the datasheet lists this pin as O but it is the analog ground connection.
11 SS passive Programmable soft-start, set by an external capacitor.
12 GND power_in Connect to ground.
13 RST_TH input Input for reset circuitry to detect undervoltage on the output, with adjustable threshold.
14 VSENSE input Feedback input for voltage-mode control, connected to the output divider.
15 COMP output Error amplifier output used for external loop compensation.
16 VReg input Internal low-side FET connection that loads the output during start-up or limits overshoot; tied to Vout.
17 PGND power_in Power ground connection for the switching stage.
18 SW bidirectional Switched drain output/input of the internal 60-V power MOSFET.
19 VIN power_in Unregulated input voltage supply pin for the boost converter.
20 BOOT passive Bootstrap capacitor pump connection.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-20-EP
Category Power Supply Chip
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Unregulated input voltages (VIN, EN, SW) VI -0.3 60 V All voltage values with respect to GND 4
Unregulated input voltages (BOOT) VI -0.3 8 V All voltage values with respect to GND 4
Regulated voltage VReg -0.3 60 V All voltage values with respect to GND 4
Logic level signals (RT, RST, SYNC, VSENSE, RST_TH) -0.3 5.5 V All voltage values with respect to GND 4
Logic level signals (SS, Cdly) -0.3 8 V All voltage values with respect to GND 4
Logic level signals (COMP) -0.3 7 V All voltage values with respect to GND 4
Operating virtual junction temperature range TJ -40 150 °C 4
Storage temperature Tstg -55 165 °C 4
Unregulated buck supply input voltage (VIN, EN) VI 3.6 40 V 4
Output voltage range VReg 2.5 50 V 4
Bootstrap capacitor (BOOT) 3.6 8 V 4
Switched outputs (SW) 3.6 52 V 4
Logic level inputs (RST, VSENSE, RST_TH, Rslew, SYNC, RT) 0 5.25 V 4
Logic level inputs (SS, Cdly, COMP) 0 6.5 V 4
Operating junction temperature range TJ -40 150 °C 4
Supply voltage on VIN line VIN 1.5 40 V Normal mode – buck mode after start up 5
Regulator output voltage VReg 50 V VSENSE = 2.5 V in boost mode 5
Feedback voltage VSENSE 2.463 2.5 2.538 V VIN = 12 V 5
Bias current, normal mode Iq-Normal 4.2 8 mA 5
Shutdown current ISD 2 4 μA EN = 0 V, VIN = 12 V, TA = 25°C 5
Duty cycle pulse width (tON-Min) tON-Min 50 100 150 ns Bench mode = 500 kHz 5
Duty cycle pulse width (tOFF-Min) tOFF-Min 50 100 150 ns Bench mode = 500 kHz 5
Switch mode frequency fsw 80 2200 kHz Set using external resistor on RT pin 5
Internal oscillator frequency fsw -10 10 % 5
Low input threshold (EN) VIL 0.7 V 5
High input threshold (EN) VIH 1.7 V 5
External capacitor charge current IO 1.4 2 2.6 μA EN = high 5
Switching threshold VThreshold 1.8 2 2.4 V Output voltage in regulation 5
POR delay timer trdly 3.6 7 ms Based on Cdly capacitor, Cdly = 4.7 nF 5
Reset threshold for VReg RST_TH 0.768 0.832 V Check RST output 5
Filter time before RST asserted low tRSTdly 10 20 35 μs Once VRST_TH or OV_TH Is detected, delay before RST Is asserted low 5
Low-level input voltage, VIL (SYNC) VIL 0.7 V 5
High-level input voltage, VIH (SYNC) VIH 1.7 V 5
Leakage current (SYNC) ILeakage 65 95 μA SYNC = 5 V 5
SYNC input clock frequency 80 2200 kHz VIN = 12 V, fsw < fext < 2 × fsw 5
Minimum duty cycle (SYNCCLK) SYNCCLK 30 % 5
Maximum duty cycle (SYNCCLK) SYNCCLK 70 % 6
Thermal shutdown junction temperature TSD 175 200 °C 6
Internal switch resistance RDS(on) 500 mΩ Measured across VSWD and GND 5
Switch current limit ICL 5.7 A VIN = 7 V to 28 V 5
Leakage into EN terminal ILeakage 35 μA EN = 24 V 5
SYNC transition, external to internal clock SYNCtrans 32 μs No external clock, VIN = 12 V 5
SYNC transition, internal to external clock SYNCtrans 2.5 μs External clock = 500 kHz, VIN = 12 V 5
Slew current IRslew 20 μA Rslew = 50 kΩ, Calculated not measured 6
Slew current IRslew 100 μA Rslew = 50 kΩ, Calculated not measured 6
Thermal shutdown hysteresis THYS 30 °C 6
Thermal resistance, junction to ambient (recommended table) θJA 35 °C/W 4
Thermal resistance, junction to case (recommended table) θJC 10 °C/W 4
Junction-to-ambient thermal resistance RθJA 43.8 °C/W PWP 20-pin package 5
Junction-to-case (top) thermal resistance RθJC(top) 21.4 °C/W PWP 20-pin package 5
Junction-to-board thermal resistance RθJB 18.5 °C/W PWP 20-pin package 5
Junction-to-top characterization parameter ψJT 0.5 °C/W PWP 20-pin package 5
Junction-to-board characterization parameter ψJB 18.3 °C/W PWP 20-pin package 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 1.2 °C/W PWP 20-pin package 5

CAD (KiCad official)

  • Symbol: TPS55332QPWPRQ1
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps55332qpwprq1-etched.step / tps55332qpwprq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps55332qpwprq1.step / tps55332qpwprq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 43d7dcf970a38188, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF