LT3741EUF#PBF from Analog Devices, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	EN/UVLO	input	Enable pin that turns on the internal bias core and subregulators at a 1.55V falling threshold with 130mV hysteresis, requires a voltage bias since it has no pull-up or pull-down, and shuts the part down fully at approximately 0.5V.
2	VREF	power_in	Buffered 2V reference output capable of 0.5mA drive.
3	CTRL2	input	Thermal control input used to reduce the regulated current level, with the lower of CTRL1 and CTRL2 setting the output current.
4	GND	power_in	Ground pin.
5	CTRL1	input	Sets the high-level regulated output current and overcurrent level, with the input internally clamped to a maximum of 1.5V and the overcurrent set 23mV above the regulated level.
6	SS	passive	Soft-start pin with an 11µA charging current that requires an external capacitor to ground to limit the regulated current during start-up.
7	FB	input	Feedback pin for voltage regulation and overvoltage protection, with a 1.21V feedback voltage; switching is prevented for 13µs when the voltage exceeds 1.5V.
8	SENSE+	input	Inverting input of the average current mode loop error amplifier, connected to the external current sense resistor RS.
9	SENSE-	input	Non-inverting input of the average current mode loop error amplifier, through which the reference current based on CTRL1 or CTRL2 flows out of the pin toward the output side of RS.
10	VC	passive	Provides compensation for the average current loop, with typical values of 20k to 50k for the resistor and 2nF to 5nF for the capacitor.
11	GND	power_in	Ground pin.
12	RT	passive	A resistor to ground sets the switching frequency between 200kHz and 1MHz; the pin is current limited to 60µA and must not be left open.
13	SYNC	input	Frequency synchronization pin; RT should be chosen for an internal clock 20% slower than the SYNC pulse frequency, and the pin should be grounded when not in use.
14	GND	power_in	Ground pin.
15	HG	output	High-side external FET gate drive output with 2.3Ω pull-up and 1.3Ω pull-down impedance.
16	SW	passive	Lower rail for the floating high-side driver that connects the two power FETs and the inductor.
17	CBOOT	power_out	Provides a floating 5V regulated supply for the high-side FET driver, charged through an external Schottky diode from VCC_INT when SW is near ground.
18	LG	output	Low-side external FET gate drive output with 2.3Ω pull-up and 1.0Ω pull-down impedance.
19	VCC_INT	power_out	Regulated 5V output for charging the CBOOT capacitor and powering digital and switching circuits, current limited to 50mA, and tied to the rail below 6V VIN.
20	VIN	power_in	Input supply pin that must be locally bypassed with a 4.7µF low-ESR capacitor to ground.
21	GND	power_in	Exposed pad, GND, that must be soldered to the PCB.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	QFN-20-EP(4x4)
Category	Power Management ICs
Pins	21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input Voltage Range	VIN	6		36	V		3
VIN Pin Quiescent Current, Non-Switching Operation	IQ		1.8	2.5	mA	Not Switching	3
VIN Pin Quiescent Current, Shutdown Mode	IQ		0.1	1	µA	VEN/UVLO = 0V, RT = 40kΩ	3
EN/UVLO Pin Falling Threshold		1.49	1.55	1.61	V		3
CTRL1 Pin Control Range		0		1.5	V		3
Reference Voltage (VREF Pin)	VREF	1.94	2	2.06	V		3
Full Range SENSE+ to SENSE-		48	51	54	mV	VCTRL1 = 1.5V	3
Regulation Voltage (VCC_INT Pin)	VCC_INT	4.7	5	5.2	V		3
Switching Frequency fSW	fSW	900	1000	1070	kHz	RT = 40kΩ	3
Switching Frequency fSW	fSW	185	200	233	kHz	RT = 200kΩ	3
Feedback Regulation Voltage	VFB	1.192	1.21	1.228	V	CTRL1 = 1.5V, ISENSE- = 23µA, VSENSE+ = 2V	3
Current Control Loop gm Amp Offset Voltage	VOS	-3	0	3	mV	VCM = 4V	4
Current Control Loop gm	gm	375	475	625	µA/V		4
VIN Voltage	VIN			40	V		2
EN/UVLO Voltage	VEN/UVLO			6	V		2
VREF Voltage	VREF			3	V		2
CTRL1 and CTRL2 Voltage	VCTRL1, VCTRL2			3	V		2
SENSE+ Voltage	VSENSE+			40	V		2
SENSE- Voltage	VSENSE-			40	V		2
VC Voltage	VC			3	V		2
SW Voltage	VSW			40	V		2
RT Voltage	VRT			3	V		2
FB Voltage	VFB			3	V		2
SS Voltage	VSS			6	V		2
VCC_INT Voltage	VCC_INT			6	V		2
SYNC Voltage	VSYNC			6	V		2
Storage Temperature Range	TSTG	-65		150	°C		2
Maximum Junction Temperature	TJMAX			125	°C	UF package (20-lead 4mm x 4mm QFN)	2
Thermal Resistance, Junction to Ambient	θJA		37		°C/W	UF package (20-lead 4mm x 4mm QFN)	2
Operating Temperature Range (E grade)	TJ	-40		125	°C	LT3741EUF#PBF, order information table	2

CAD (KiCad official)

Symbol: LT3741EUF#PBF
Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
3D model files: lt3741euf-pbf-etched.step / lt3741euf-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt3741euf-pbf.step / lt3741euf-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (24 pp, sha256 ffd25fe12b4612d5, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

LT3741EUF#PBF

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3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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