TPS56339DDCT from Texas Instruments, in a TSOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Ground pin, the source terminal of the low-side MOSFET and ground for the controller circuit, and sensitive FB must be connected to this GND at a single point.
2	SW	output	Switch node connection between the high-side MOSFET and the low-side MOSFET.
3	VIN	power_in	Input voltage supply pin and the drain terminal of the high-side MOSFET.
4	FB	input	Converter feedback input, connected to the output voltage through a feedback resistor divider.
5	EN	input	Enable pin that floats to enable, and the input undervoltage lockout is adjusted with two resistors.
6	BOOT	output	A 30-Ω boot resistor and a 0.1-μF bootstrap capacitor are required between BOOT and SW, and this capacitor carries the gate drive voltage for the high-side MOSFET.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSOT-23-6
Category	Power Management (PMIC)
Pins	6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage VIN	VIN	-0.3		26	V		4
Input voltage EN	EN	-0.3		6	V		4
Input voltage BOOT	BOOT	-0.3			V	max printed as SW+6	4
Input voltage FB	FB	-0.3		6	V		4
Output voltage BOOT-SW	BOOT-SW	-0.3		6	V		4
Output voltage SW	SW	-0.3		26	V		4
SW transient voltage	SW	-3		26	V	<10 ns transient	4
Operating junction temperature	TJ	-40		150	°C		4
Storage temperature	Tstg	-65		150	°C		4
Input voltage VIN	VIN	4.5		24	V		4
Input voltage EN	EN	-0.1		5.5	V		4
Input voltage FB	FB	-0.1		5.5	V		4
Output voltage BOOT-SW	BOOT-SW	-0.1		5.5	V		4
Output voltage SW	SW	-0.1		24	V		4
Output current	IOUT	0		3	A		4
Operating junction temperature	TJ	-40		125	°C		4
Input voltage operation	VIN	4.5		24	V		5
VIN UVLO rising threshold	VIN_UVLO	3.9	4.2	4.4	V	VIN rising threshold	5
VIN UVLO falling threshold	VIN_UVLO	3.5	3.7	3.9	V	VIN falling threshold	5
EN rising threshold	VEN_RISE	1.18		1.28	V	EN rising threshold	5
EN falling threshold	VEN_FALL	1.08	1.12		V	EN falling threshold	5
Reference voltage at TJ = 25 °C	VREF	0.79	0.802	0.814	V	TJ = 25 °C	5
Reference voltage over temperature	VREF	0.782	0.802	0.822	V	TJ = -40 °C to 125 °C	5
High-side MOSFET current limit	IHS_LIMIT	3.9	4.7	5.4	A		5
Low-side MOSFET current limit	ILS_LIMIT	2.7	3.6	4.7	A	VIN = 12 V	5
Switching frequency	fSW	420	500	600	KHz		5
Junction-to-ambient thermal resistance	RθJA		119.1		°C/W	simulated on JEDEC board	4
Junction-to-case (top) thermal resistance	RθJC(top)		58.1		°C/W		4
Junction-to-board thermal resistance	RθJB		36.7		°C/W		4
Junction-to-top characterization parameter	ΨJT		9.4		°C/W		5
Junction-to-board characterization parameter	ΨJB		36.2		°C/W		5

CAD (KiCad official)

Symbol: TPS56339DDCT
Footprint: Package_TO_SOT_SMD:TSOT-23-6
3D model: TSOT-23-6 (KiCad packages3D, STEP)
3D model files: tps56339ddct-etched.step / tps56339ddct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps56339ddct.step / tps56339ddct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (32 pp, sha256 f74e7982b0b81390, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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TPS56339DDCT

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3D Model

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