component
LM5066PMH
Public Made by Adomby adom
Texas Instruments Surge Protection Devices (SPDs), HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownLM5066PMH
Texas Instruments · Surge Protection Devices (SPDs) · HTSSOP-28-EP
LM5066PMH from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | input | Output rail sense connection (external MOSFET source) used to determine MOSFET VDS for power limiting and to monitor output voltage; absolute maximum 100 V to GND. |
| 2 | GATE | output | Gate drive output that connects to the external MOSFET gate; absolute maximum 100 V to GND and 1 kV HBM ESD rating. |
| 3 | SENSE | input | Current sense input; the voltage across the sense resistor RSNS is measured from VIN_K to this pin, and absolute maximum is 100 V to GND and ±0.3 V to VIN_K. |
| 4 | VIN_K | power_in | Positive supply Kelvin pin on which the input voltage is measured, and the sense-resistor connection on the high side of RSNS. |
| 5 | VIN | power_in | Input supply connection for the device; recommended operating range 10 V to 80 V, absolute maximum 100 V to GND. |
| 6 | N/C | unconnected | No connection. |
| 7 | UVLO/EN | input | Undervoltage lockout and enable input set by an external divider from VIN, with 20-µA hysteresis current and nominal enable threshold of 2.48 V; can be used for remote shutdown. |
| 8 | OVLO | input | Overvoltage lockout input set by an external divider from VIN, with 21-µA hysteresis current and disable threshold of 2.46 V. |
| 9 | AGND | power_in | Analog device ground; connect to GND at the pin. |
| 10 | GND | power_in | Circuit ground for the device. |
| 11 | SDAI | input | SMBus data input pin; connect to SDAO if unidirectional isolation devices are not required. |
| 12 | SDAO | output | SMBus data output pin; connect to SDAI if unidirectional isolation devices are not required. |
| 13 | SCL | input | SMBus clock pin. |
| 14 | SMBA | output | SMBus alert pin, active low. |
| 15 | VREF | power_in | Internally generated precision reference for analog-to-digital conversion; connect a 1-µF capacitor to ground for bypassing (nominal 2.97 V per the VREF dropout note). |
| 16 | DIODE | passive | Connect to a diode-configured MMBT3904 NPN transistor for remote temperature monitoring; leave grounded if temperature measurement is not used. |
| 17 | VAUX | input | Auxiliary voltage input for telemetry from an external source with full-scale input of 2.97 V. |
| 18 | ADR2 | tri_state | SMBus address line 2; tri-state input that should be connected to GND, VDD, or left floating. |
| 19 | ADR1 | tri_state | SMBus address line 1; tri-state input that should be connected to GND, VDD, or left floating. |
| 20 | ADR0 | tri_state | SMBus address line 0; tri-state input that should be connected to GND, VDD, or left floating. |
| 21 | VDD | power_out | Internal sub-regulator output of nominally 4.85 V (4.9 V in the feature description); connect a 1-µF ceramic capacitor to ground and do not load with other ICs, current-limited to 30 mA. |
| 22 | CL | input | Current limit range select: connect to GND or leave floating for a 50-mV overcurrent threshold, or connect to VDD for 26 mV. |
| 23 | FB | input | Power good feedback input; an external divider from the output sets the PGD switching point, with a nominal threshold of 2.46 V and 20-µA hysteresis current. |
| 24 | RETRY | input | Fault retry configuration input: connected to GND or floating gives continuous retry during a fault, while connection to VDD latches the device off after a fault. |
| 25 | TIMER | passive | Timing capacitor pin that sets insertion time delay, fault timeout period, and restart timing; the fault discharge threshold is 3.9 V. |
| 26 | PWR | input | Power limit set: an external resistor from this pin, together with RSNS, sets the maximum power dissipation allowed in the series pass MOSFET. |
| 27 | N/C | unconnected | No connection. |
| 28 | PGD | output | Open-drain power good output that is high when FB is above VFBTH (nominally 2.46 V) and VIN is within its UVLO and OVLO thresholds; the drain tolerates 80 V off-state and 100 V transients, so pull up to a suitable voltage. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28-EP |
| Category | Circuit Protection |
| Pins | 29 |
CAD (KiCad official)
- Symbol:
LM5066PMH - Footprint:
Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm - 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files:
lm5066pmh-etched.step/lm5066pmh-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5066pmh.step/lm5066pmh.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (66 pp, sha256
cbb1347886195422, retrieved 2026-10-10, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).